經過2天的努力，一個大工程的時序終於調好了。之前對時序分析總是有畏懼心理，這兩天靜下心來，通過查閱資料，不斷測試，終於消除了所有錯誤
放個之前的圖片
主要是用到了調整邏輯、約束時序的方法
create_clock -period 25.000 -name clk_main -waveform {0.000 12.500} [get_ports i_global_clk]
create_clock -period 25.000 -name clk_cfg -waveform {0.000 12.500} [get_pins design_1_i/processing_system7_0/inst/FCLK_CLK0]
create_clock -period 50.000 -name clk_20 -waveform {0.000 25.000} [get_nets u_usb30_top/CLK_20M]
create_clock -period 25.000 -name clk_40 -waveform {0.000 12.500} [get_nets u_usb30_top/CLK_40M]
##false path
set_false_path -from [get_clocks -of_objects [get_pins u_usb30_top/u_clk_rst_gen/u_clk_syn/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks clk_cfg]
set_false_path -from [get_clocks -of_objects [get_pins u_usb30_top/u_clk_rst_gen/u_clk_syn/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks clk_cfg]
set_multicycle_path -setup -from [get_clocks clk_20] -to [get_clocks -of_objects [get_pins u_usb30_top/u_clk_rst_gen/u_clk_syn/inst/mmcm_adv_inst/CLKOUT0]] 3
set_multicycle_path -hold -end -from [get_clocks clk_20] -to [get_clocks -of_objects [get_pins u_usb30_top/u_clk_rst_gen/u_clk_syn/inst/mmcm_adv_inst/CLKOUT0]] 2
set_multicycle_path -setup -start -from [get_clocks clk_40] -to [get_clocks -of_objects [get_pins u_usb30_top/u_clk_rst_gen/u_clk_syn/inst/mmcm_adv_inst/CLKOUT1]] 3
set_multicycle_path -hold -from [get_clocks clk_40] -to [get_clocks -of_objects [get_pins u_usb30_top/u_clk_rst_gen/u_clk_syn/inst/mmcm_adv_inst/CLKOUT1]] 2