set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
將這三句添加到時序約束文件（沒有創建一個），即可解決Vivado未分配引腳約束報錯的問題
————————————————
版權聲明：本文為CSDN博主「暖暖的時間回憶」的原創文章，遵循CC 4.0 BY-SA版權協議，轉載請附上原文出處鏈接及本聲明。
原文鏈接：https://blog.csdn.net/qq_36248682/article/details/105300860
set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]
以上語句三選一，怎么選看實際需求。通常我都選最后一條，未使用引腳懸空。
————————————————
版權聲明：本文為CSDN博主「請叫我凍凍」的原創文章，遵循CC 4.0 BY-SA版權協議，轉載請附上原文出處鏈接及本聲明。
原文鏈接：https://blog.csdn.net/dimples_Song/article/details/81326747
[DRC UCIO-1] Unconstrained Logical Port: 12 out of 161 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: SPI_1_0_ss1_o, SPI_1_0_ss2_o, SPI_0_0_ss1_o, SPI_0_0_ss2_o, SDIO_0_0_busvolt[2:0], SDIO_0_0_buspow, SDIO_0_0_cdn, SDIO_0_0_clk_fb, SDIO_0_0_led, and SDIO_0_0_wp.