原理介紹
1、分頻
FPGA設計中時鍾分頻是重要的基礎知識，對於分頻通常是利用計數器來實現想要的時鍾頻率，由此可知分頻后的頻率周期更大。一般而言實現偶數系數的分頻在程序設計上較為容易，而奇數分頻則相對復雜一些，小數分頻則更難一些。
1）偶分頻系數=時鍾輸入頻率/時鍾輸出頻率=50MHz/5MHz=10，則計數器在輸入時鍾的上升沿或者下降沿從0~（10-1）計數，而輸出時鍾在計數到4和9時翻轉。
2）奇分頻系數=50MHz/10MHz=5，則兩個計數器分別在輸入時鍾的上升沿和下降沿從0~ （5-1）計數，而相應的上升沿和下降沿觸發的輸出時鍾在計數到1和4時翻轉，最后將兩個輸出時鍾進行或運算從而得到占空比為50%的5分頻輸出時鍾。
下圖所示為50MHz輸入時鍾進行10分頻和5分頻的仿真波形
2、倍頻
兩種思路：PLL（鎖相環）或者利用門延時來搭建
注意：此仿真是利用FPGA內部電路延遲來實現的倍頻需要在后仿真下才能看到波形，在行為仿真下無法得到輸出波形。
一、時鍾IP的分頻倍頻相關參數說明
輸入時鍾：clk_in1(125MHz)
輸出時鍾：clk_out1(50MHz)，clk_out2(74.25MHz)
則VCO Freq=1262.5MHz=clk_in1*CLKFBOUT_MULT_F/DIVCLK_DIVIDE=125*50.5/5
clk_out1(50MHz)=VCO_Freq/Divide=1265.5/25.250
clk_out2(74.25MHz)=VCO_Freq/Divide=1265.5/17
二、MMCME4_ADV
MMCME4是一種混合信號塊，用於支持頻率合成、時鍾網絡設計和減少抖動。基於相同的VCO頻率，時鍾輸出可以有單獨的分頻、相移和占空比。此外，MMCME4還支持動態移相和分數除法
（1）Verilog 初始化模板
MMCME4_ADV #(
.BANDWIDTH("OPTIMIZED"), // Jitter programming
.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB
.CLKFBOUT_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKIN1_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKIN2_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0
.CLKOUT0_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT1_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT1_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT2_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT2_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT3_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT3_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT3_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT4_CASCADE("FALSE"), // Divide amount for CLKOUT (1-128)
.CLKOUT4_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT4_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT4_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT5_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT5_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT5_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT6_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT6_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT6_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT6_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.COMPENSATION("AUTO"), // Clock input compensation
.DIVCLK_DIVIDE(1), // Master division value
.IS_CLKFBIN_INVERTED(1'b0), // Optional inversion for CLKFBIN
.IS_CLKIN1_INVERTED(1'b0), // Optional inversion for CLKIN1
.IS_CLKIN2_INVERTED(1'b0), // Optional inversion for CLKIN2
.IS_CLKINSEL_INVERTED(1'b0), // Optional inversion for CLKINSEL
.IS_PSEN_INVERTED(1'b0), // Optional inversion for PSEN
.IS_PSINCDEC_INVERTED(1'b0), // Optional inversion for PSINCDEC
.IS_PWRDWN_INVERTED(1'b0), // Optional inversion for PWRDWN
.IS_RST_INVERTED(1'b0), // Optional inversion for RST
.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999).
.REF_JITTER2(0.0), // Reference input jitter in UI (0.000-0.999).
.SS_EN("FALSE"), // Enables spread spectrum
.SS_MODE("CENTER_HIGH"), // Spread spectrum frequency deviation and the spread type
.SS_MOD_PERIOD(10000), // Spread spectrum modulation period (ns)
.STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked
)
MMCME4_ADV_inst (
.CDDCDONE(CDDCDONE), // 1-bit output: Clock dynamic divide done
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
.CLKFBSTOPPED(CLKFBSTOPPED), // 1-bit output: Feedback clock stopped
.CLKINSTOPPED(CLKINSTOPPED), // 1-bit output: Input clock stopped
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6
.DO(DO), // 16-bit output: DRP data output
.DRDY(DRDY), // 1-bit output: DRP ready
.LOCKED(LOCKED), // 1-bit output: LOCK
.PSDONE(PSDONE), // 1-bit output: Phase shift done
.CDDCREQ(CDDCREQ), // 1-bit input: Request to dynamic divide clock
.CLKFBIN(CLKFBIN), // 1-bit input: Feedback clock
.CLKIN1(CLKIN1), // 1-bit input: Primary clock
.CLKIN2(CLKIN2), // 1-bit input: Secondary clock
.CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
.DADDR(DADDR), // 7-bit input: DRP address
.DCLK(DCLK), // 1-bit input: DRP clock
.DEN(DEN), // 1-bit input: DRP enable
.DI(DI), // 16-bit input: DRP data input
.DWE(DWE), // 1-bit input: DRP write enable
.PSCLK(PSCLK), // 1-bit input: Phase shift clock
.PSEN(PSEN), // 1-bit input: Phase shift enable
.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement
.PWRDWN(PWRDWN), // 1-bit input: Power-down
.RST(RST) // 1-bit input: Reset
);
（2）本實驗仿真所用參數配置說明及部分端口調用
1、參數配置說明
本實驗通過輸入時鍾CLKIN1(150MHz)，實現輸出反饋時鍾CLKFBOUT(150MHz)、輸出時鍾CLKOUT0(74.25MHz)、輸出時鍾CLKOUT1(74.25MHz)、輸出時鍾CLKOUT2(59.4MHz)、輸出時鍾CLKOUT3(49.5MHz)。其關鍵參數設置如下
CLKFBOUT_MULT_F（1.98） //指定如果需要不同的頻率，則對相關的CLKOUT時鍾輸出進行分數分割的乘法系數。這個數字與CLKFBOUT_MULT_F和DIVCLK_DIVIDE值的組合將決定輸出頻率
DIVCLK_DIVIDE（1） // 指定所有輸出時鍾相對於輸入時鍾的除法因子
CLKOUT0_DIVIDE_F(4)、 CLKOUT1_DIVIDE(4)、CLKOUT2_DIVIDE(5)、CLKOUT3_DIVIDE(6) //指定分頻輸出的除法因子從而輸出不同的頻率
注：輸入150MHz 乘以倍頻因子1.98，得到倍頻頻率297MHz ，由於DIVCLK_DIVIDE（1）設置為1，則分頻的參考時鍾為297/1=297；輸出反饋時鍾也為：297/1=297；那么其它CLKOUT_DIVIDE_F、CLKOUT1_DIVIDE~CLKOUT6_DIVIDE的分頻根據設置的分頻系數結合分頻參考時鍾297MHz而定，即參考分頻時鍾/相應分頻系數，比如這里的297/4；297/5；297/6。其仿真波形如下圖1所示
圖1
圖2所示的波形仿真是改變了此參數設置：DIVCLK_DIVIDE(2)
圖2
2、端口調用
MMCME4_ADV #(
.BANDWIDTH("OPTIMIZED"), // Jitter programming (HIGH, LOW, OPTIMIZED)
.CLKFBOUT_MULT_F(1.98), //
.CLKFBOUT_PHASE(0.0), //
.CLKIN1_PERIOD(6.6),
.CLKOUT0_DIVIDE_F(4), //
.CLKOUT1_DIVIDE(4),
.CLKOUT2_DIVIDE(5),
.CLKOUT3_DIVIDE(6),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.DIVCLK_DIVIDE(2), // Master division value (1-106)
.REF_JITTER1 (0.100)
)
MMCME4_ADV_inst (
// Clock Outputs outputs: User configurable clock outputs
.CLKOUT0(i_byte_clk), // 1-bit output: CLKOUT0
.CLKOUT0B(), // 1-bit output: Inverted CLKOUT0
.CLKOUT1(i_pix_clk74m25), // 1-bit output:
.CLKOUT1B(), // 1-bit output: Inverted CLKOUT1
.CLKOUT2(i_pix_clk59m4), // 1-bit output: CLKOUT2
.CLKOUT2B(), // 1-bit output: Inverted CLKOUT2
.CLKOUT3(i_pix_clk49m5), // 1-bit output: CLKOUT3
.CLKOUT3B(), // 1-bit output: Inverted CLKOUT3
// Feedback outputs: Clock feedback ports
.CLKFBOUT(mmcm_ser_ref_clk), // 1-bit output: Feedback clock
.CLKFBOUTB(), // 1-bit output: Inverted CLKFBOUT
// Status Ports outputs: MMCM status ports
.LOCKED(cmt_locked), // 1-bit output: LOCK
// Clock Inputs inputs: Clock inputs
.CLKIN1(clk150_g), // 1-bit input: Primary clock
// Control Ports inputs: MMCM control ports
.PWRDWN(1'b0), // 1-bit input: Power-down
.RST(i_ref_clk_rst) // 1-bit input: Reset
);
附：UltraScale+的高級混合模式時鍾管理的三種原語庫
MMCME3_ADV
The MMCME3 is a mixed signal block designed to support frequency synthesis, clock network
deskew, and jitter reduction. The clock outputs can each have an individual divide, phase shift
and duty cycle based on the same VCO frequency. Additionally, the MMCME3 supports dynamic
phase shifting and fractional divides.
MMCME3_BASE
The MMCME3 is a mixed signal block designed to support frequency synthesis, clock network
deskew, phase adjustment and jitter reduction. The MMCME3_BASE supports a subset of the
more common features and thus is easier to instantiate and use compared to the full features
MMCME3_ADV.
MMCME4_ADV
The MMCME4 is a mixed signal block designed to support frequency synthesis, clock network
deskew, and jitter reduction; The clock outputs can each have an individual divide, phase shif
and duty cycle based on the same VCO frequency. Additionally, the MMCME4 supports dynamic
phase shifting and fractional divides.