VCS仿真 Dump Memory

---

兩種方法

• vcs聯合verdi生成fsdb文件
• vcs生成vpd文件

VCS聯合verdi生成fsdb文件

1.testbench中加入如下語句：

initial begin
     $fsdbDumpfile("tb.fsdb");
     $fsdbDumpvars;
end

always@(posedge clk)
begin
  $fsdbDumpMDA(R1); //每個時鍾dump出mem的值，verdi記錄值的變化
  $fsdbDumpMDA(R2);
end

2.注意調用 vcs -debug_pp 開始仿真

3.測試使用的verilog代碼與仿真腳本

testbench

`timescale 1ns/100ps

module Testbench;

  reg          clk;

  integer      i;
  reg          R1[7:0];
  reg [3:0]    R2[7:0];

  initial  begin
    clk = 0;  

	for (i=0; i<8; i=i+1) begin
	  R1[i] = 1'b0;
	  R2[i] = 4'h0;
	end

	#10;

	for (i=0; i<8; i=i+1) begin
	  R1[i] = $random;
	  R2[i] = $random;
	end

    repeat(5) @(posedge clk);

	for (i=0; i<8; i=i+1) begin
	  R1[i] = $random;
	  R2[i] = $random;
	end

    repeat(60) @(posedge clk);
    $finish;
  end

always #200 clk = ~clk;

initial begin
     $fsdbDumpfile("tb.fsdb");
     $fsdbDumpvars;
end

always@(posedge clk)
begin
  $fsdbDumpMDA(R1); //每個時鍾dump出mem的值，verdi記錄值的變化
  $fsdbDumpMDA(R2);
end


endmodule

注意:此處僅是示范dumpMemory，實際中需要每一個時鍾沿都需dump數據

vcs仿真腳本

#!/bin/bash -f

export NOVAS_HOME="/EDA/Synopsys/verdi/vJ-2014.12-SP2"
export NOVAS_PLI="${NOVAS_HOME}/share/PLI/VCS/LINUX64"
export LD_LIBRARY_PATH="$NOVAS_PLI"

export NOVAS="${NOVAS_HOME}/share/PLI/VCS/LINUX64"

export novas_args="-P $NOVAS/novas.tab   $NOVAS/pli.a "

vcs +v2k -sverilog +vcs+lic+wait -full64 -debug_pp \
       +warn=noCDNYI,noIPDW,noILLGO,noTMR,noPHNE,noIRIID-W \
       -Mupdate +notimingcheck +nospecify \
       ${novas_args}\
       -f file.f \

./simv

4.使用Verdi查看結果

verdi 打開波形文件，選擇>>Tool>>Memory/MDA

5.截圖(verdi)

vcs生成vpd文件

1.lab文件

testbench

`timescale 1ns/100ps

module Testbench;

  reg          clk;

  integer      i;
  reg          R1[7:0];
  reg [3:0]    R2[7:0];

  initial  begin
    clk = 0;  

	for (i=0; i<8; i=i+1) begin
	  R1[i] = 1'b0;
	  R2[i] = 4'h0;
	end

	#10;

	for (i=0; i<8; i=i+1) begin
	  R1[i] = $random;
	  R2[i] = $random;
	end

    repeat(5) @(posedge clk);

	for (i=0; i<8; i=i+1) begin
	  R1[i] = $random;
	  R2[i] = $random;
	end

    repeat(60) @(posedge clk);
    $finish;
  end

always #200 clk = ~clk;

initial begin
  $vcdpluson();
end

always@(posedge clk)
begin
    $vcdplusmemon();
end

endmodule

vcs腳本

vcs -full64 Testbench.v  -debug_pp +vcd+vcdpluson

./simv

2.截圖(dve)

參考文獻

http://www.edaboard.com/thread59624.html

verdi3手冊