xilinx FPGA普通IO作PLL時鍾輸入

在xilinx ZC7020的片子上做的實驗;

[結論]

普通IO不能直接作PLL的時鍾輸入,專用時鍾管腳可以;

普通IO可以通過BUFG再連到PLL的時鍾輸入上,但要修改PLL的設置 input clk的選項中要選擇"No Buffer";

具體內部布局分配可以通過 Xilinx的FPGA Editor來查看,

ZYNQ的時鍾管理也和之前的片子略有不同,之后在另一篇介紹,相關文檔 <ug472_7Series_Clocking.pdf>

[Demo1]

// demo1 two bufg connect

module iobuf(

 input clk,

 input     rst,

 output   led

 );

 wire clkin_w;

 BUFG BUFG_inst (

      .O(clkin_w),           // Clock buffer output

      .I(clk)                   // Clock buffer input

   );

 pll0 u_pll0(

    .CLK_IN1(clkin_w),      // IN

    .CLK_OUT1(clkout),  // OUT

    .RESET(rst));       // IN

assign led = clkout;

endmodule

鎖相環PLL默認輸入前端有個BUFG單元,而兩個BUFG不能相連,所以會報這樣的錯:

ERROR:NgdBuild:770 - IBUFG 'u_pll0/clkin1_buf' and BUFG 'BUFG_inst' on net

   'clkin_w' are lined up in series. Buffers of the same direction cannot be

   placed in series.

ERROR:NgdBuild:924 - input pad net 'clkin_w' is driving non-buffer primitives:

 [Demo2]

// demo2 regular io directly connect to PLL

module iobuf(

    input clk,

 input     rst,

 output   led

 );
 wire clkin_w;

 /*

 BUFG BUFG_inst (

      .O(clkin_w),           // Clock buffer output

      .I(clk)                   // Clock buffer input

   );

*/

 pll0 u_pll0(

    .CLK_IN1(clk),      // IN

    .CLK_OUT1(clkout),  // OUT

    .RESET(rst));       // IN

assign led = clkout;

endmodule

普通IO不能直接做鎖相環的輸入,所以會報這樣的錯:

ERROR:Place:1397 -  A clock IOB / MMCM clock component pair have been found that

   are not placed at an optimal clock IOB / MMCM site pair. The clock IOB

   component <clk> is placed at site <A18>. The corresponding MMCM component

   <u_pll0/mmcm_adv_inst> is placed at site <MMCME2_ADV_X0Y0>. The clock IO can

   use the fast path between the IOB and the MMCM if the IOB is placed on a

   Clock Capable IOB site that has dedicated fast path to MMCM sites within the

   same clock region. You may want to analyze why this problem exists and

   correct it. If this sub optimal condition is acceptable for this design, you

   may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this

   message to a WARNING and allow your design to continue. However, the use of

   this override is highly discouraged as it may lead to very poor timing

   results. It is recommended that this error condition be corrected in the

   design. A list of all the COMP.PINs used in this clock placement rule is

ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

如果有ucf中加上這句約束:

NET clk          CLOCK_DEDICATED_ROUTE = FALSE;

依舊會報錯,在ZYNQ7000系列,這樣還是通不過,如下:

ERROR:PhysDesignRules:2256 - Unsupported MMCME2_ADV configuration. The signal

   u_pll0/clkin1 on the CLKIN1 pin of MMCME2_ADV comp u_pll0/mmcm_adv_inst with

   COMPENSATION mode ZHOLD must be driven by a clock capable IOB.

ERROR:Pack:1642 - Errors in physical DRC.

使用普通的IO,再連接bufg來連到時鍾線上,

仍會報這樣的錯誤,因為還是兩bufg相連了:

ERROR:NgdBuild:770 - IBUFG 'u_pll0/clkin1_buf' and BUFG 'BUFG_inst' on net

   'clkin_w' are lined up in series. Buffers of the same direction cannot be

   placed in series.

ERROR:NgdBuild:924 - input pad net 'clkin_w' is driving non-buffer primitives:

  [Demo3]

// dem3 regular io with BUFG then connect to PLL which with"No Buffer" setting

 module iobuf(

 input clk,

 input     rst,

 output   led

 );

 wire clkin_w;

 BUFG BUFG_inst (

      .O(clkin_w),           // Clock buffer output

      .I(clk)                   // Clock buffer input

   );

 pll0 u_pll0(

    .CLK_IN1(clkin_w),      // IN

    .CLK_OUT1(clkout),  // OUT

    .RESET(rst));       // IN

assign led = clkout;

endmodule

PLL的設置如下圖,

這樣普通IO就可以當作PLL的時鍾輸入了,順利產生bit;

時鍾還是最好用全局時鍾IO,畫圖時一定要注意:)

zc702里沒有global clock的概念了,但有了很多專用時鍾腳,用起來一樣;