https://www.tutorialspoint.com/digital_circuits/index.htm
Number Systems, Base Conversions, Binary Numbers Representation, Signed Binary Arithmetic, Codes, Error Detection & Correction Codes, Boolean Algebra, Canonical and Standard Forms, K-Map Method, Quine-McCluskey Tabular Method, Logic Gates, Two-Level Logic Realization, Combinational Circuits
[LDOCE][牛津] the canon of Holy Scripture:《聖經》的真經; canonical是canon的形容詞，不是cannon(大炮)的。
canonical: 1. according to canon law; 2. in the simplest mathematical form
Arithmetic Circuits
Half adder is a combinational circuit, which performs the addition of two binary numbers A and B are of single bit. We can implement its functions with 2-input Ex-OR gate & 2-input AND gate. function: 功能; 函數 Ex-OR, XOR: Exclusive OR. ex-wife的ex-: Latin 'out of, from'
Full adder performs the addition of three bits A, B and Cin. Where, A & B are the two parallel significant bits and Cin is the carry bit, which is generated from previous stage. carry: 多出來的位要 攜帶, 搬運, 傳送, 運送。A 4-bit binary adder performs the addition of two 4-bit numbers.
We can implement any higher order binary adder just by cascading the required number of Full adders. (C0=0). This binary adder is also called as ripple carry binary adder because the carry propagates ripples from one stage to the next stage.
The subtraction of two binary numbers A and B can be written as, A - B = (2′s complimento f B) = A + (1′s compliment of B) + 1. To get 1's complement of a binary number, invert the given number. To get 2's complement of it, invert it and add 1 to the least significant bit (LSB) of given result. For example:
3 - 2 = 011 - 010 = 011 + 101 + 001 = 001
2 - 3 = 010 + 100 + 001 = 111 (-1)
or:
2 - 3 = 2 + (-3) = 010 + (~011 + 001)
So the operation of a subtractor is similar to that of an adder internally. (C0=1)
complement(ary) angle: 余角(90°), supplement(ary) angle: 補角，The inverse of a number is defined as the number created by interchanging the face value (from left to right) and index of digits of number, The opposite of a number is a number that is the same distance from 0 as another number, but in the opposite direction. Given a number, the opposite of that number can also be thought of as the number that needs to be added in order for the result to be 0, The reciprocal of any quantity is, one divided by that quantity.
Decoder is a combinational circuit that has 'n' input lines and maximum of 2^n output lines. One of these outputs will be active High based on the combination of inputs present, when the decoder is enabled. That means decoder detects a particular code. 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0. One of these four outputs will be '1' for each combination of inputs when enable, E is '1'. An Encoder is a combinational circuit that performs the reverse operation of Decoder.
Multiplexer has maximum of 2^n data inputs, 'n' selection lines and single output line. One of these data inputs will be connected to the output based on the values of selection lines. 4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y. 從內部接線來看，input和output可能connect着。把Multiplexer看作個黑盒子或者C語言里的函數，那么數據從input pass到output.
De-Multiplexer performs the reverse operation of Multiplexer. It has single input, 'n' selection lines and maximum of 2^n outputs. The input will be connected to one of these outputs based on the values of selection lines. 1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four outputs Y3, Y2, Y1 &Y0. invert, inverse, revert, reverse有何不同？前文翻轉二進制位用了invert，此段功能顛倒用了reverse. [柯林斯] Inverted commas are punctuation marks that are used in writing to show where speech or a quotation begins and ends. They are usually written or printed as `'". [LDOCE] If a vehicle or its driver reverses, they go backwards.
Programmable Logic Devices (PLDs) are integrated circuits. They contain an array [不要看到array就想到數組。 陳列, 一系列, 部署] of AND gates and another array of OR gates. There are three kinds of PLDs based on the type of array(s), which has programmable feature.
1. Programmable Read Only Memory (PROM)
2. Programmable Array Logic (PAL)
3. Programmable Logic Array (PLA)
Memory里存邏輯聽起來別扭，真值表順耳。
function buy_a_new_phone(have_money, too_old, lost) { return have_money && (too_old || lost) }
function buy_a_new_phone(i, j, k) { static const bool tbl[2][2][2] = { ... }; return tbl[i][j][k]; }
函數可以返回32/64位的int，估計硬件可以"return" 7~80位。組合爆炸，2^32=40億。
版本1的機器代碼也是串二進制位，binary information，但這種搞法好像算CPU了？We need decoders to access PLDs?
The threshold gate contains at least one input and only one output. Additionally, it contains the respective weights to each input and a threshold value. 聽起來像機器學習里的神經元？https://victorzhou.com/blog/intro-to-neural-networks/
訓練的時候weight要變，online用訓練好的模型時才有用？
This sequential circuit contains a set of inputs and outputs. The outputs of sequential circuit depends not only on the combination of present inputs but also on the previous outputs. Previous output is nothing but the present state. Therefore, sequential circuits contain combinational circuits along with memory storage elements. Some sequential circuits may not contain combinational circuits, but only memory elements.
There are two types of memory elements based on the type of triggering that is suitable to operate it.
1. Latches, level sensitive, Set Reset (SR), Data (D)
2. Flip-flops (called a trigger circuit by IBM), edge sensitive, SR, D, JK, T
We can convert one flip-flop into the remaining three flip-flops by including some additional logic. So, there will be total of twelve flip-flop conversions.
A flip-flop can store one-bit of information. In order to store multiple bits of information, we require multiple flip-flops. The group of flip-flops, which are used to hold store the binary data is known as register.
Have you signed the hotel register? cash register: 收銀機。
file: a set of papers; (存放文件公文卷宗檔案等的)抽屜架子夾子封皮箱子等。
If the register is capable of shifting bits either towards right hand side or towards left hand side is known as shift register. Serial/Parallel In - Serial/Parallel Out Shift Registers. Shift registers are used as Parallel to serial converters, Serial to parallel converters, Sequence generators, and Counters. The Serial In - Parallel Out SIPO shift register accepts the data from outside in serial form and it requires 'N' clock pulses in order to shift 'N' bit data. Johnson Ring counter is also called as Twisted Ring counter and switch tail Ring counter.
Synchronous sequential circuits change affect their states for every positive ornegative transition of the clock signal based on the input. So, this behavior of synchronous sequential circuits can be represented in the graphical form and it is known as state diagram. A synchronous sequential circuit is also called as Finite State Machine FSM, if it has finite number of states.
Regular expressions describe patterns which can be recognized by finite state machines (FSM). It is possible to algorithmically construct a FSM that corresponds to a given regular expression. A FSM can be described by a transition table (program), which can be represented by a string.
"What is the difference between finite automata and finite state machines?" [stackexchange] In FSM for circuit designs the input signal is mostly assumed to be a bit (binary), whereas in finite state automata one can have a general "abstract" alphabet of input symbols.
"What is a Truing machine?" https://introcs.cs.princeton.edu/java/52turing/
There are two types of FSMs.
1. Mealy State Machine, outputs depend on both present inputs & present states.
2. Moore State Machine, outputs depend only on present states.
Microprocessor technology has dramatically changed since 1971, when Intel's 4004 CPU ran at a mere 740 KHz and contained only 2,250 transistors using a 10 micrometer process. [不算內存？]
"Intel 4004 simulator/emulator", 我記得有個在屏幕上顯示電路圖，電線會變紅的，Java寫的，但找不着了。我記得很清楚的是：我沒看懂。:-)
六級/考研單詞: convert, arithmetic, detect, algebra, logic, holy, script, cannon, accord, mathematics, implement, parallel, propagate, subtract, compliment, complement, invert, reverse, data, comma, integrate, array, static, threshold, respective, blog, offline, thereby, trigger, multiple, serial, pulse, twist, affection, transition, diagram, finite, regulate, construct, correspond, differentiate, abstract, alphabet, mere, transistor, ax, halt
abacus [Date: 1300-1400; Language: Latin; Origin: Greek 'flat piece of stone']
compute [Date: 1600-1700; Language: Latin; ... 'to think']
calculate: [Date: 1500-1600; Language: Latin; Origin: ... from calculus 'stone used in counting']
suanpan: [Origin: Chinese, "Isn't that obvious?"]
kowtow詞典里有，TBBT里老外也說。congee, wok ...
1001如何？64位內存(ENIAC 200個word; byte: a biteful of bits). 4條8位的定長指令，數據寬度5位，最高位為符號位，jlz: 小於0則跳轉。所謂內存，用Latch來搭，the /ðiː/ register. ax, cx, c, ip (instruction pointer)都是它部分位的別名。
雖然下面犯了許多錯誤，我還是編了個程序的：1001-asm-imitator.py - Fun_with_Words - 博客園 (cnblogs.com)
2~3個寄存器，7~8條指令，按時鍾單步，高電平的線用紅色顯示。下面是我能做的；
mov ax, 1
mov cx, 9
add ax, 1
add cx, -1
jlz -2 ; 向上跳兩條指令。-16位也行？
halt
上面是胡說，接着再八道。電腦是怎么think的？不對此有點了解，覺得自己在玩真空中的球形雞。不考慮電氣等因素，專注於邏輯。level sensitive的Latch適合我們，可顯示為個黑盒子:
byte access_register(byte addr) { return fake[addr]; } 或者分成兩個bank { return (bank0[addr] << 4) | bank1[addr]; }, 或者每個bank 1位，電路圖上就不要顯示內部了。上電后CPU並不開始run，而是可以搬動開關設置reigster: init_register(byte data[16]); 然后hit the button: while(1) on_clock();
function on_clock() {
for (;;)
if (all gates are refreshed) break
for g in all_gates:
if (g.refreshed) continue;
if (g所依賴的，或者說g的輸入是它的輸出的, gate們 都refresh了) g.on_clock();
Five_bits_Full_adder::on_clock() { out = in0 + in1; refreshed = 1; } // 知道加法器的原理后把它當黑盒子用就好了，也別顯示內部。
function connect(gate_out, pin_out, gate_in, pin_in) // 生成網表，記錄依賴關系(圖?)
the register的每一位用個燈，或者顯示1/0，最好像那種鍾表，一個輪子上印着0和1，聲效像機場通知牌。
然后設計個語言VSLI (Very Simple Logic Indeed)，用flex和bison給它做個stuff，能把用像Verilog那樣的語言描述的stuff變成仿真器/模擬器要用的stuff. 當然Verilog和VSLI天差地別，而且前者說不定能導出網表，但不會是txt格式吧？不用VSLI而是C++也行，但我覺得會有許多啰嗦的語句描述pin屬於哪個gate. VSLI的好處還有：還可以用它設計別的CPU啊，比如程序和數據分開的哈弗架構？
匯編器不用做，我可以手撕匯編和機器碼，做點力所能及的事。
mov ax, 1 00 0 00001
mov cx, 9 00 1 01001
add ax, 1 01 0 00001
add cx, -1 01 1 11111
jlz -2 10 11110 ; 哦哦，忘了沒有reg_idx, 那用位吧，可以省幾個移位寄存器。
halt 11 000000
把Latch作為整體回避了循環依賴問題。avoid, eschew.
# AndGate
in A, B
out C
[C=A+B]
上面描述了一個器件，#長得就像個長腳的盒子, [盒子里的邏輯]。也可以：
#0
AB
1
[1=+AB]
0類器件有兩個輸入，一個輸出，表達式用波蘭式，這樣的格式可以手撕。
> AndGate.1.C OrGate.3.A
> 0.0.2 1.0.0
第1個AndGate的C接3號或門的A，前者輸出，后者輸入。
我們這個initiative，能掙8個月到88歲的人的錢，請耐心往下看。軟件免費送，賣硬件。48位的程序，軟件有按鈕可以改（起碼可以改改數)，硬件不顯示(寫死)。ax, cx共10位，軟硬件都顯示。按clock單步，軟件顯示接線上的高電平（可調速度），硬件不顯示。硬件可以取巧：按一下按鈕把燈顯示對就行了，你管我內部怎么實現。每執行一條指令，機器就轉移下狀態。4條指令不是4個狀態，而是多個。人不能兩次跨過同一條河流，add ax, 1會執行多次。粉燈版賣給女寶寶，藍燈版男寶寶，機械版，鍍金版，地鼠版 [我家孩子8個月就會調程序了:-)] 中學可以拿它做教具，對着程序講，硬件增加48個開關。書《如何手撕CPU》。面包板、萬用表、示波器、邏輯分析儀——給賣這些個的收費帶貨。不賣嘎，賣知識。這個能賣到全世界。Together, we coin the word suanpan. 醋有了，就等餃子了。:-)
gate_1_C = gate_1_A + gate_1_B
gate_2_A = gate_1_C
...
那豈不是就剩兩步：1. 寫哪些賦值語句; 2. 以什么樣的順序執行。在python或javascript里eval()下？
對我來說，把指令放在ROM里比寄存器里反而好理解點。訪問內存時，CPU的一個cycle需要幾個clock.
def read_mem(a7, a6, a5, a4, a3, a2, a1, a0): reurn rom[.....]; 每個數組元素是個8位的tuple，試了下寫起來好累。
CPU應該也算個狀態機。fetch_instruction: a7 = x; a6 =x ; ... a0=x; 硬件是8根線一起過去。然后放在latch里？譯碼用decoder? "算術單元"得有根enable線？enable時才加，線是始終接着的？way out of my league啊。Search(the Simplest CPU design)，學習中…… program counter怎么設初值呢？得和reset線接在一起吧：a=!reset & (....), reset是1是必為0, reset是0時沒影響。b=reset | (...), reset是1時必為1。re-set里面有個set，頭一次是set，以后是set again. 是不是得有個“內部總線”? 手工調整賦值語句順序，仿真器不必解決依賴關系?
哦，少了條jmp指令啊，so humiliating, embarrassing. 嗯，hlt改jlz 0, 哦，還有別的錯誤……