實驗8 #第8章 Verilog有限狀態機設計-1 #Verilog #Quartus #modelsim


8-1 流水燈控制器

1. 實驗要求:采用有限狀態機設計彩燈控制器,控制LED燈實現預想的演示花型。

2. 實驗內容:

    (1)功能:設計彩燈控制器,要求控制18個LED燈實現如下的演示花型:

  • 從兩邊往中間逐個亮,全滅;
  • 從中間往兩頭逐個亮,全滅;
  • 循環執行上述過程;         

2.1 流水燈控制器用兩個always語句時間,條理更清晰。源碼如下:

 

 1 //water lamp
 2 //2020-10-16
 3 //by YongFengXie
 4 module water_lamp(clk,rst_n,lamp);
 5 input clk;
 6 input rst_n;
 7 output reg [17:0] lamp;
 8 
 9 reg [4:0] state;
10 parameter s0=5'b00000,  // all 0
11           s1=5'b00001,  // light from edge to middle
12           s2=5'b00011,
13           s3=5'b00010,
14           s4=5'b00110,
15           s5=5'b00111,
16           s6=5'b00101,
17           s7=5'b00100,
18           s8=5'b01100,
19           s9=5'b01101,    // all 1
20           s10=5'b01111,   //all 00
21           s11=5'b01110,  // light from middle to edge
22           s12=5'b01010,
23           s13=5'b01011,
24           s14=5'b01001,
25           s15=5'b01000,
26           s16=5'b11000,
27           s17=5'b11001,
28           s18=5'b11011,
29           s19=5'b11010;  // all 1
30 
31 always @(posedge clk or negedge rst_n)  // state transition
32 begin
33   if(~rst_n)
34     state<=s0;
35   else case(state)
36          s0:state<=s1;
37          s1:state<=s2;
38          s2:state<=s3;
39          s3:state<=s4;
40          s4:state<=s5;
41          s5:state<=s6;
42          s6:state<=s7;
43          s7:state<=s8;
44          s8:state<=s9;
45          s9:state<=s10;
46          s10:state<=s11;
47          s11:state<=s12;
48          s12:state<=s13;
49          s13:state<=s14;
50          s14:state<=s15;
51          s15:state<=s16;
52          s16:state<=s17;
53          s17:state<=s18;
54          s18:state<=s19;
55          s19:state<=s0;
56          default:state<=s0;
57        endcase
58 end
59 
60 always @(state)      // demonstration pattern
61 begin
62   case(state)
63     s0:lamp<=18'b000_000_000_000_000_000;
64     s1:lamp<=18'b100_000_000_000_000_001;  
65     s2:lamp<=18'b110_000_000_000_000_011;  
66     s3:lamp<=18'b111_000_000_000_000_111;
67     s4:lamp<=18'b111_100_000_000_001_111;
68     s5:lamp<=18'b111_110_000_000_011_111;
69     s6:lamp<=18'b111_111_000_000_111_111;
70     s7:lamp<=18'b111_111_100_001_111_111;
71     s8:lamp<=18'b111_111_110_011_111_111;
72     s9:lamp<=18'b111_111_111_111_111_111;
73     s10:lamp<=18'b000_000_000_000_000_000;
74     s11:lamp<=18'b000_000_001_100_000_000;
75     s12:lamp<=18'b000_000_011_110_000_000;
76     s13:lamp<=18'b000_000_111_111_000_000;
77     s14:lamp<=18'b000_001_111_111_100_000;
78     s15:lamp<=18'b000_011_111_111_110_000;
79     s16:lamp<=18'b000_111_111_111_111_000;
80     s17:lamp<=18'b001_111_111_111_111_100;
81     s18:lamp<=18'b011_111_111_111_111_110;
82     s19:lamp<=18'b011_111_111_111_111_110;
83     default:lamp<=18'b000_000_000_000_000_000;
84   endcase
85 end
86 
87 endmodule
88  

 

2.2 流水燈控制電路的測試代碼如下:

 1 //water lamp testbench
 2 //2020-10-16
 3 //by YongFengXie
 4 module water_lamp_tb;
 5 reg clk;
 6 reg rst_n;
 7 wire [17:0] lamp;
 8 
 9 water_lamp ub(clk,rst_n,lamp);
10 
11 initial begin
12           clk=1'b0;
13           rst_n=1'b0;
14           #20 rst_n=1'b1;
15           #1000 $stop;
16         end
17 
18 always #5 clk=~clk;
19 
20 endmodule 

2.3 流水燈花型演示電路的ModelSim仿真結果如圖2-1,圖2-2所示:

 

      圖2-1 流水燈仿真結果1

 

    圖2-2 流水燈仿真結果2

2.4 總結:流水燈控制電路的設計,或者說花型演示,規划好花型的個數,即狀態,剩下就是純體力活,這里狀態編碼嘗試用了格雷碼,畢竟

     誤碼跳變的概率小,當然書上(王金明 數字系統設計與Verilog HDL 7th ,page 230)用的順序碼。


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