RT，否則警告Warning: Tri-state node(s) do not directly drive top-level pin(s)，會利用或門代替中間的扇出fan-out.
原因：在進行FPGA設計時，對於FPGA內部的信號不能出現被賦值為高阻的狀態，只有頂層的信號，即輸出的信號才可以賦值為高阻態。
找出這個信號，然后把賦值為x'bz改為x'b0或x'b1(具體是改為x'b0還是x'b1要根據實際情況確定,x也行)。
CAUSE: The design contains tri-state nodes that drive non-tri-state logic, but the chip does not support internal tri-states. As a result, the Quartus II software converts all the tri-state nodes feeding internal logic to an equivalent logic.
ACTION: Avoid this warning by either removing the non-tri-state fan-outs of the affected tri-state nodes or replacing the tri-state nodes with non-tri-state logic.
實例：
module tri_state (input oe1, data1, in, output out, output bidir);
wire tribuf;
assign tribuf = oe1 ? data1 : 1'bz;
and(out, in, tribuf);
assign bidir = tribuf;
endmodule
Warning: Tri-state node(s) do not directly drive top-level pin(s)
Warning: Converted the fan-out from the tri-state buffer "tribuf" to the node "comb" into an OR gate
RTL視圖：
Technology Map Viewer:
CAUSE:The specified tri-statebuffer feeds internal logic in addition to feeding tri-statelogic, but the chip does not support internal tri-states. As a result, the Quartus II software converts the non-tri-statefan-out(s) of the tri-statebuffer to an ORgate.
Consider the following design:
module test1 (input oe1, data1, in, output out, inout bidir);
wire tribuf, tmp;
assign tribuf = oe1 ? data1 : 1'bz;
and(tmp, in, tribuf);
assign bidir = tribuf;
assign out = tmp;
endmodule
Here, the tri-statebuffer tribufhas fan-outs to both the tri-stateand non-tri-statenodes. As a result, the fan-out to the non-tri-statenode is converted to !oe1 + data1.
Note that an inversion also counts as non-tri-statelogic. So, the node tribufin the design test2is also converted to an ORgate.
module test2 (input oe1, data1, output out, inout bidir);
wire tribuf;
assign tribuf = oe1 ? data1 : 1'bz;
assign bidir = tribuf;
assign out = !tribuf;
endmodule
Additionally, a tri-statebuffer feeding the output enable signal of another tri-statebuffer is also converted to logic.
Consider the following Verilog design:
module test3 (input oe1, data1, data2, inout bidir);
wire tribuf1, tribuf2;
assign tribuf1 = oe1 ? data1 : 1'bz;
assign tribuf2 = tribuf1 ? data2 : 1'bz;
assign bidir = tribuf2;
endmodule
Here, the tri-statebuffer tribuf1is converted to an ORgate.
ACTION:Avoid this warning by either removing the non-tri-statefan-out of the tri-statebuffer or replacing the tri-statebuffer with non-tri-statelogic.