Timing Analysis in the Design Flow
設計流程中的時序分析
在設計流程的不同階段，時序分析有不同的目的。在DC中，時序驅動着用於綜合的庫單元的選擇以及數據路徑中的組合邏輯之間的寄存器的分配。在ICC中，時序驅動着單元的布局和互連線的布局，以實現關鍵路徑上的延遲最小化。在PT中，詳細的簽核(sign-off)時序分析是該工具的主要目的。這些工具共同使用者同樣的基礎延遲計算方法。時序分析的結果在通常情況下是一致的，但不總是完全相同的。因為PT是一個簽核(sign-off)時序分析工具，它會進行更加全面透徹的分析去驗證正確的時序，而DC與ICC工作時，以滿足驅動綜合，物理實現，以及優化的足夠精度為目標即可。
Timing analysis serves different purposes in different phases of the design flow. In Design Compiler, timing drives the selection of library cells used for synthesis and the allocation of registers between combinational logic in data paths. In IC Compiler, timing drives the placement of cells and the routing of interconnections to minimize delays in the critical paths.In PrimeTime, exhaustive sign-off timing analysis is the main purpose of the tool.These tools all share the same basic delay calculation methods. The timing results are generally consistent between the tools but not always identical. Because PrimeTime is a sign-off analysis tool, it performs a more comprehensive and exhaustive analysis to verify correct timing, whereas Design Compiler and IC Compiler perform timing analysis with sufficient accuracy to drive synthesis, physical implementation, and optimization.
synopsys 設計約束命令
Synopsys Design Constraint Commands
DC，ICC和PT有許多共同的時間分析功能。這些工具允許您使用相同的命令來指定時序約束和生成時序報告。這些命令稱為Synopsys設計約束(SDC)。這些命令具有相同的語法，並在所有支持的工具中產生相同的效果。這意味着您可以使用相同的SDC腳本在DC、ICC、PT和其他工具中約束設計。SDC命令可以指定設計規則約束、功率約束以及時間約束。
Design Compiler, IC Compiler, and PrimeTime share many common timing analysis features. The tools allow you to use the same commands to specify timing constraints and generate timing reports. These commands are known as the Synopsys Design Constraints (SDC). These commands have the same syntax and produce the same effects across all the supported tools. That means you can use the same SDC script to constrain a design in Design Compiler, IC Compiler, PrimeTime, and other tools. The SDC commands can specify design rule constraints and power constraints as well as timing constraints.
在每個工具中，可以用write_sdc命令寫出一個腳本，該腳本包含一組SDC命令，這些命令在當前設計上設定約束。在另一種工具中，可以使用read_sdc命令讀取文件並應用相同的約束。read_sdc命令的工作方式與source命令非常相似，但是read_sdccommand也會檢查腳本命令是否符合SDC規則。SDC腳本文件可以用於在Synopsys工具和某些外部工具之間傳輸約束。
In each tool, the write_sdc command writes out a script containing a set of SDC commands that specify the current constraints set on the design. In a different tool, you can use the read_sdc command to read in the file and apply the same constraints. The read_sdc command works very much like the source command, but the read_sdccommand also checks the script commands for SDC compliance. SDC script files can be used to transfer constraints between Synopsys tools and also certain external tools.
一些Synopsys工具以擴展命令或命令選項的形式擴展了SDC所支持的約束功能。write_sdc命令只寫出與sdc兼容的命令，這些命令可以在任意SDC格式兼容的工具上執行。而write_script命令會寫出更大范圍的用於設置設計屬性的指令。
Some Synopsys tools have extended constraint capabilities beyond what is supported by SDC in the form of additional commands or command options. The write_sdc command writes out only the SDC-compatible commands, which can be executed in any SDC-compatible tool. The write_script command writes out a wider range of commands that set the design attributes.
為了幫助追蹤已設置的約束，一些SDC命令可允許將注釋字符串與約束關聯。要添加注釋，需使用-commentoption 選項注釋字符串。例如，命令行> create_clock -name"CLK"-周期 0.33 -注釋"Main clock"。注釋在整個設計、分析和實現流程中都得到保留。每次使用write_sdc或write_script命令時，該工具使用相同的注釋字符串使用-comment選項寫出SDC命令。
To help keep track of constraints that have been set, some SDC commands optionally allow a comment string to be associated with the constraint. To add a comment, use the -commentoption along with a comment string. For example,
prompt> create_clock -name "CLK" -period 0.33 -comment "Main clock"
The comment is maintained throughout the design, analysis, and implementation flow. Each time you use the write_sdc or write_script command, the tool writes out the SDC command with the -comment option using the same comment string.
要從設計中刪除所有的synopsys設計約束，可以使用remove_sdc命令。表1-1列出了用於指定時間約束和與時間相關的設計特性的SDC命令。有關SDC命令的更多信息，請參見使用Synopsys設計約束格式應用手冊，它可以在SolvNet的Design Compiler、IC Compiler和PrimeTime文檔集中找到。要訪問SolvNet，請訪問SolvNet的網頁，網址如下: https://solvnet.synopsys.com
To remove all Synopsys Design Constraints from the design, use the remove_sdc command.Table 1-1 lists the SDC commands used for specifying timing constraints and timing-related design characteristics. For more information about SDC commands, see the Using the Synopsys Design Constraints Format Application Note, which is available on SolvNet in the documentation sets for Design Compiler, IC Compiler, and PrimeTime. To access SolvNet, go to the SolvNet Web page at the following address: https://solvnet.synopsys.com
表1-1 SDC時序命令
Table 1-1 SDC Timing Commands
| Command/命令 |
Usage/用法 |
用法中文說明 |
| create_clock |
Specifies the clocks used in the design and their characteristics: |
指定在設計中使用的時鍾及其特性:名稱、周期、波形和在設計中的位置。時間分析器需要此信息來確定每個路徑端點所需的數據到達時間。 |
| prompt> create_clock "PHI1" -period 10 -waveform {5.0 9.5} |
||
| group_path |
Groups a set of paths or endpoints for timing analysis and cost |
對一組路徑或端點進行分組，以便進行時序分析和（時間）花銷函數計算。包含在一個組內路徑的分析和優化是獨立於其他組的。默認情況下，每個時鍾有一個路徑組。 |
| prompt> group_path -name "group1" -weight 2.0 -to {CLK1A CLK1B} |
||
| set_clock_gating_check |
Creates one or more clock-gating checks in the design. A |
在設計中創建一個或多個時鍾控制檢查。時鍾門控檢查是對時鍾門控單元的控制輸入執行的建立或保持時間檢查。它檢測發生了時鍾邊緣截斷或假時鍾脈沖。 |
| prompt> set_clock_gating_check -setup 0.75 -hold 0.5 |
||
| set_clock_groups |
Specifies groups of clocks that are mutually exclusive or |
指定互相排斥或異步的時鍾組。這可以防止分析從一個時鍾組開始到另一個時鍾組結束的時序路徑。 |
| set_clock_groups -asynchronous -name g1 -group CLK1 -group CLK2 |
||
| set_clock_latency |
Specifies explicitly the source latency or network latency of a clock. This command is typically used before layout, when propagated clocking cannot be used. Source latency is the time the clock signal takes to be propagated from its ideal waveform origin point to the clock definition point in the design. Network latency is the time the clock signal takes to be propagated from the clock definition point in the design to the clock pin of the sequential device. The timing analyzer uses this information to determine clock arrival times in the absence of propagated clocking. |
顯式指定時鍾的源延遲或網絡延遲。此命令通常在布局之前使用，此時經過傳播后的時鍾信息還無法獲得。源延遲是時鍾信號從理想波形點傳播到設計中的時鍾定義點所需的時間。網絡延遲是時鍾信號從設計中的時鍾定義點傳播到時序設備的時鍾pin的時間。在沒有傳播時鍾的情況下，定時分析器使用此信息來確定時鍾到達時間。 |
| prompt> set_clock_latency 1.2 -rise [get_clocks CLK1] prompt> set_clock_latency 0.9 -fall [get_clocks CLK1] |
||
| set_clock_sense |
Specifies the unateness of a clock signal, either positive or negative,that is propagated past a nonunate point in the clock network. A nonunate point is a place where the sense of the clock signal cannot be determined, such as the output of an exclusive OR gate with the clock signal as one input and an unknown side-input value as the other input. |
指定時鍾信號(正的或負的)的不適當性，該時鍾信號在時鍾網絡中傳播過一個nonunate點。nonunate點是一個時鍾信號的感覺不能被確定的地方，例如一個時鍾信號作為一個輸入和一個未知的邊輸入值作為另一個輸入的排他性或門的輸出。 |
| set_clock_sense -positive -clocks [get_clocks CLK1] XOR/Z |
||
| set_clock_transition |
Specifies explicitly the rising or falling transition times of a clock. This command is typically used before layout, when propagated clocking cannot be used. The transition time applies to rising or falling transitions at the clock pins of sequential devices clocked by the specified clock. The timing analyzer uses this information to |
顯式指定時鍾的上升或下降轉換時間。此命令通常在布局之前使用，此時經過傳播后的時鍾信息還無法獲得。該過渡時間適用於由指定時鍾計時的順序設備的時鍾插腳處的上升或下降過渡。在沒有傳播時鍾的情況下，定時分析器使用此信息來確定時鍾轉換時間 |
| set_clock_transition 0.75 CLK |
||
| set_clock_uncertainty |
Specifies the uncertainty or skew characteristics of a single clock or |
指定單個時鍾或兩個不同時鍾之間的不確定性或偏移特性。對於一個時鍾，簡單的不確定性是連續的邊緣之間的最大差異的變化遠離名義到達時間。對於兩個時鍾，時鍾間不確定度是時鍾邊緣出現時相對於標稱到達時間的變化的最大差異或歪斜。時序分析儀使用此信息來確定每次定時檢查的最壞時鍾到達時間。 |
| prompt> set_clock_uncertainty -setup 0.65 [get_clocks CLK] prompt> set_clock_uncertainty -hold 0.45 [get_clocks CLK] |
||
| set_data_check |
Creates a custom data-to-data check, also known as a nonsequential constraint, using specified setup and hold time values between the specified data signals. You specify the "from" object or related pin, the "to" object or constrained pin, and the setup or hold value for the check |
使用指定的數據信號之間的建立與保持時間值，創建自定義數據至數據路徑的檢查，也稱為非順序約束。您可以指定"from"對象或相關pin、"to"對象或約束pin以及用於檢查的建立時間或h保持時間值 |
| prompt> set_data_check -rise_from and1/B -to and1/A 0.4 |
||
| set_disable_timing |
Disables timing checks and timing optimization for specified cells, |
禁用指定單元格、引腳或端口的定時檢查和定時優化。這個命令完全從時間分析中刪除受影響的對象，這與set_false_path命令不同，set_false_path命令只從路徑中刪除時序約束，而不刪除延遲計算。如果通過一個引腳的所有路徑都為假，set_disable_timing比set_false_path更有效。 |
| set_disable_timing {U2 U3} |
||
| set_driving_cell |
Specifies the name of a library cell that drives one or more input ports of the design. This information allows the timing analyzer to |
指定驅動設計的一個或多個輸入端口的庫單元的名稱。這些信息允許定時分析儀准確地確定由驅動程序、負載和網絡的線特性引起的延遲。 |
| prompt> set_driving_cell -lib_cell INV -pin Z -library tech_lib [all_inputs] |
||
| set_fanout_load |
Specifies the number of external loads in the fanout of one or more |
指定設計的一個或多個輸出端口扇出中的外部負載數量。該工具使用這些信息來執行最大扇出設計規則，而不是執行時間分析。 |
| prompt> set_fanout_load 2 all_outputs() |
||
| set_ideal_latency |
Specifies explicitly the ideal clock latency in the transitive fanout of |
顯式指定指定端口或引腳的傳遞扇形中的理想時鍾延遲。理想時鍾延時是一個時鍾信號從它的理想波形原點傳播到一個理想網絡中順序設備的時鍾針所需要的時間。默認的理想延遲為零。在沒有傳播時鍾的情況下，定時分析工具使用理想延遲來確定時鍾到達時間。 |
| prompt> set_ideal_latency 1.2 -rise {A B C} prompt> set_ideal_latency 0.9 -fall {A B C} |
||
| set_ideal_network |
Invokes ideal clocking behavior in the transitive fanout of specified |
在指定端口、引腳或網絡的傳遞扇形中調用理想的時鍾行為，導致在指定的整個網絡中顯式指定的延遲和轉換時間(默認為零)。理想時鍾在布局之前使用，當傳播時鍾不能使用時。 |
| prompt> set_ideal_network {port1 port2} |
||
| set_ideal_transition |
Specifies explicitly the rising or falling transition times of signals in the transitive fanout of specified ports or pins. The default ideal transition time is zero. The timing analysis tool uses the ideal transition time in the absence of propagated clocking. |
顯式指定在指定端口或引腳的傳遞扇形中信號的上升或下降過渡時間。默認的理想過渡時間為零。定時分析工具在沒有傳播時鍾的情況下使用理想的轉換時間。 |
| prompt> set_ideal_transition 1.2 -rise {A B C} |
||
| set_input_delay |
Specifies the amount of delay from a launch clock edge outside of the design to the arrival of data at an input of the design. This information is necessary to check the timing of signals entering the design inputs. |
指定從設計之外的發射時鍾邊緣到數據到達設計的輸入端的延遲量。這些信息對於檢查進入設計輸入信號的時間是必要的。 |
| prompt> set_input_delay 2.3 {IN1 IN2} prompt> set_input_delay 1.2 -clock [get_clocks CLK1] [all_inputs] |
||
| set_input_transition |
Specifies explicitly the rise or fall transition times on input ports of the design for propagated (not ideal) clocking. The timing analyzer uses this information to determine the delays and transition times of signals in the transitive fanout of the input. |
為傳播(不是理想的)時鍾顯式指定設計的輸入端口上的上升或下降過渡時間。定時分析儀使用這些信息來確定輸入信號的傳遞扇形的延遲和過渡時間。 |
| prompt> set_input_transition 7.0 {A B C} |
||
| set_load |
Specifies explicitly the capacitive load on one or more input ports, |
顯式指定一個或多個輸入端口、輸出端口或網絡上的電容負載。定時分析儀使用這些信息來確定負載對信號通過端口或網絡的延遲和轉換時間的影響。 |
| prompt> set_load -subtract_pin_load 3 U1/U2/NET3 prompt> set_load -wire_load 5 the_answer |
||
| set_operating_conditions |
Specifies the operating conditions under which the design is |
說明在設計分析和優化的操作條件。庫定義了操作條件，每個條件由一組工藝、溫度和電壓值組成。庫中的每個單元對於每個操作條件都有一組不同的單元定時特性。該命令根據名稱選擇這些定義的操作條件中的一個或多個，並調用最佳情況/最差情況分析或片上變化分析。 |
| prompt> set_operating_conditions -min BCIND -max WCIND -library other_lib_core |
||
| set_output_delay |
Specifies the amount of delay from the departure of data at an output of the design to the capture clock edge outside the design. This information is necessary to check the timing of signals leaving the design outputs. |
指定從設計輸出的數據離開到設計之外的捕獲時鍾邊緣的延遲量。這些信息對於檢查離開設計輸出信號的時間是必要的。 |
| prompt> set_output_delay 1.7 -clock [get_clocks CLK1] [all_outputs] |
||
| set_port_fanout_number |
Specifies the number of external loads in the fanout of one or more |
指定設計的一個或多個輸出端口扇出中的外部負載數量。這允許定時分析儀估計連接到輸出的外部設備的總線負載。 |
| prompt> set_port_fanout_number 5 [get_ports O1] |
||
| set_propagated_clock |
Causes network latency to be determined by propagating delays |
使網絡延遲由傳播延遲通過時鍾網絡為指定的時鍾或為過渡離開指定的端口或針。當詳細的網RC信息可用時，傳播的時鍾可以在布局之后使用。 |
| prompt> set_propagated_clock [all_clocks] |
||
| set_resistance |
Specifies explicitly the resistance of one or more nets. The timing |
顯式指定一個或多個網的電阻。時序分析器使用這些信息來確定在延遲和過渡電阻的影響時間的信號通過。 |
| prompt> set_resistance 200 {a b} |
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| set_timing_derate |
Applies derating or adjustment factors to specified delays of timing |
對時間檢查的指定延遲應用減損或調整因素。降額可以用來模擬過程、電壓和溫度變化的最壞情況的影響。 |
| prompt> set_timing_derate -max -early -net_delay 0.9 |
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| set_wire_load_model |
Specifies the types of wire load models used for estimating wire |
指定在執行布線之前用於估計線阻和電容的線負載模型的類型。用於設計編譯器和黃金時間;不用於使用拓撲模式的DC或ICC環境中。 |
| prompt> set_wire_load_model -name "10x10" -library my_lib.db |
||
Library Timing Data
庫時序數據
為了進行時序分析，該工具需要得到設計中使用的邏輯單元的時序特性的信息，如組合邏輯塊的輸入輸出延遲;時序模塊的時鍾到輸出延遲、建立時間和保持時間;和單元輸出信號的轉換時間。單元的時序特性包含在每個單元的庫描述中。時序分析工具可以以以下形式讀取庫數據:
•使用read_lib命令的Liberty (.lib)格式
•使用read_db或read_file命令格式化Synopsys數據庫(.db)
To perform timing analysis, the tool needs information about the timing characteristics of the logic cells used in the design, such as the input-to-output delays of combinational logic blocks; clock-to-output delays, setup times, and hold times of sequential blocks; and transition times of cell output signals. The cell timing characteristics are contained in the library description of each cell. Timing analysis tools can read the library data in the following forms:
• Liberty (.lib) format using the read_lib command
• Synopsys database (.db) format using the read_db or read_file command
單元時序特性通常使用一個特性描述工具(如Liberty NCX)與電路模擬器(如HSPICE)相結合來確定。Liberty NCX以Liberty (.lib)格式輸出單元時間數據，這是一種人們可以讀取的文本格式。一些時序分析工具可以使用read_lib命令直接讀取.lib文件。庫編譯器（LB）通常將Liberty (.lib)格式的庫編譯為Synopsys數據庫(.db)格式。db文件是一種二進制格式，比.lib格式更緊湊，讀取速度更快。時序分析工具可以通過read_db命令直接讀取.db庫，也可以通過link_library變量設置隱式讀取。每個單元時序參數，如輸入到輸出的延遲或輸出轉換時間，是輸入擺率和輸出負載的函數。因此，延遲信息被組織在與輸入擺率和輸出負載的不同組合相對應的值的表中。如果該表可用，您可以在.lib庫文件中查看時序參數表。您還可以使用report_lib -timing命令在分析工具中查看計時數據。例如：
The cell timing characteristics are typically determined by a characterization tool such as Liberty NCX in combination with a circuit simulator such as HSPICE. Liberty NCX writes out the cell timing data in Liberty (.lib) format, a text format that a person can read. Some timing analysis tools can read .lib files directly with the read_lib command. Libraries in Liberty (.lib) format are typically compiled into Synopsys database (.db) format by Library Compiler. The .db file is a binary format that is more compact and faster to read than the .lib format. A timing analysis tool can read in a .db library directly with the read_db command or implicitly via the link_library variable setting.Each cell timing parameter, such as input-to-output delay or output transition time, is a function of the input slew and output load. Accordingly, the delay information is organized in a table of values corresponding to different combinations of input slew and output load. You can view the timing parameter tables in the .lib library file, if available. You can also view the timing data in the analysis tool by using the report_lib -timing command. For example,
prompt> report_lib -timing cb13fs120_max nd02d1
...
Lookup Table Template:
Template_name
--------------------------------------------------------------------
del_1_5_7_w
VARIABLE_1: input_net_transition
VARIABLE_2: total_output_net_capacitance
INDEX_1: 0.0150 0.2500 0.6500 1.4000 3.0000
INDEX_2: 0.0000 0.0070 0.0140 0.0385 0.0805 0.1505 0.3500
...
DELAY: A2, ZN, prop, neg_unate, '', ( , ), ( , ), ( , );
cell_rise ( del_1_5_7_w ) :
VALUES : 0.0270 0.0480 0.0690 0.1400 0.2620 0.4650
1.0420 0.0680 0.0990 0.1230 0.1950 0.3160
0.5190 1.0970 0.1010 0.1510 0.1890 0.2870
0.4110 0.6140 1.1910 0.1380 0.2080 0.2630
0.4060 0.5790 0.7920 1.3670 0.1880 0.2860
0.3620 0.5660 0.8170 1.1270 1.7480
該表列出了從輸入A2到輸出ZN的上升信號的延遲值，以及從索引表中獲取的輸入過渡時間和輸出電容負載的每個可能組合。延遲計算器使用插值或外推來獲得索引表之間或外部的輸入轉換時間和電容負載的延遲值。類似的表將輸出轉換時間指定為輸入轉換和輸出加載的函數。為一個單元計算的輸出轉換時間將成為計時路徑中下一個單元的輸入轉換時間。對於設計中特定單元實例或網絡的延遲計算的詳細描述，可以使用report_delay_calculation命令。例如,
The table lists the delay values from the input A2 to the output ZN for a rising signal, for each possible combination of an input transition time and an output capacitive load taken from the index tables. The delay calculator uses interpolation or extrapolation to get delay values for input transition times and capacitive loads between or outside of the index tables. Similar tables specify the output transition times as a function of input transition and output load. The output transition time calculated for a cell becomes the input transition time for the next cell in the timing path.For a detailed description of the delay calculation for a particular cell instance or net in the design, you can use the report_delay_calculation command. For example,
prompt> report_delay_calculation -from I_RISC_CORE/I_ALU/U27/A2 \
-to I_RISC_CORE/I_ALU/U27/ZN
...
Rise Delay
cell delay = 0.0583731
Table is indexed by
(X) input_pin_transition = 0.103374
(Y) output_net_total_cap = 0.00451049
Relevant portion of lookup table:
(X) 0.0150 (X) 0.2500
(Y) 0.0000 (Z) 0.0270 (Z) 0.0680
(Y) 0.0070 (Z) 0.0480 (Z) 0.0990
Z = A + B*X + C*Y + D*X*Y
A = 0.0244 B = 0.1745
C = 2.9088 D = 6.0790
Z = 0.0583731
scaling result for operating conditions
multiplying by 1 gives 0.0583731
...
單元延遲隨運行條件的不同而不同，因此庫對於不同的運行條件角可能有不同的延遲值。條件角是電壓、溫度和工藝值(PVT)的特殊組合。一些庫是為縮放而設計的，以便分析工具可以通過在定義的操作條件及其對應的延遲值之間進行插值來獲得中間操作條件下的准確延遲值。
Cell delays vary with operating conditions, so the libraries may have different delay values for different operating condition corners. A corner is a particular combination of voltage, temperature, and process values（PVT）. Some libraries are designed for scaling so that the analysis tool can obtain accurate delay values at intermediate operating conditions by using interpolation between the defined operating conditions and their corresponding delay values.
Design Compiler
DC是一個用於將RTL（寄存器傳輸級）描述的設計轉換為門級網表的工具。DC所執行的綜合過程主要包括下列步驟：
•讀入Verilog或VHDL格式的RTL描述。
•以Synopsys設計約束（SDC）格式讀取時序，面積和功率約束。
•使用通用布爾邏輯門生成設計邏輯，優化邏輯，然后使用目標庫中指定工藝的門將設計映射到網表中。
•以.ddc格式寫出已編譯的門級網表。
Design Compiler is a synthesis tool that converts a design description at the Register Transfer Level (RTL) to a gate-level netlist. The synthesis process performed by Design Compiler typically consists of the following major steps:
• Read in the RTL description in Verilog or VHDL format.
• Read in the timing, area, and power constraints in Synopsys Design Constraints (SDC) format.
• Generate the design logic using generic Boolean gates, optimize the logic, and map the design into a netlist using the technology-specific gates of the target library.
• Write out the compiled gate-level netlist in .ddc format.
盡管面積和功率限制很重要，但只有時序限制必須絕對滿足才能使電路工作。 時序驅動邏輯實現和從庫中選擇門，以確保時序路徑延遲不超過適用的時鍾周期。 例如，在發現設置延遲過長的情況下，Design Compiler可能會使用具有更大驅動強度的大型設備來減少凈延遲，但會占用更多的面積。
Although the area and power constraints are important, only the timing constraints must be absolutely satisfied for the circuit to operate. Timing drives the logic implementation and selection of gates from the library to ensure that timing path delays do not exceed the applicable clock periods. For example, where a setup delay is found to be too long, Design Compiler might use larger devices with more drive strength to reduce net delays, at the expense of more area.
在將時序約束應用於設計之后，應使用check_timing命令檢查時序約束和設置問題。 綜合完成后，您可以報告最壞情況的路徑，並使用report_constraintand report_timing命令進行詳細分析。
After you apply the timing constraints to the design, you should check for timing constraint and setup problems with the check_timing command. After synthesis is completed, you can report the worst-case paths and analyze them in detail with the report_constraintand report_timing commands.
理想時鍾
Ideal Clocking
在布局之前的邏輯綜合階段，執行時鍾樹綜合是不切實際的，因為導線長度未知，並且時鍾偏斜對寄生互連差異非常敏感。 默認情況下，Design Compiler使用理想的時鍾，這意味着所有時鍾信號的等待時間為零，不確定性為零，過渡時間為零。 延遲是從時鍾源到時鍾寄存器引腳的延遲，對於零時鍾，理想時鍾基於零電阻和時鍾網絡電容的假設為零。 時鍾網絡中的所有網絡和單元都會自動標記為dont_touch。 理想的網絡在合成過程中沒有得到優化或緩沖。 理想的時鍾非常樂觀。 為了獲得更准確的時序結果，您可以為時鍾信號指定非零延遲，不確定性和轉換時間，以代表完整時鍾網絡預期的近似時序值。 例如，
At the logic synthesis stage before layout, performing clock tree synthesis is not practical because the wire lengths are unknown and the clock skew is highly sensitive to parasitic interconnect differences. By default, Design Compiler uses ideal clocking, which means zero latency, zero uncertainty, and zero transition time for all clock signals. Latency is the delay from the clock source to the clock register pins, which is zero for ideal clocking, based on the assumption of zero resistance and capacitance of the clock network. All nets and cells in the
clock network are automatically marked as dont_touch. Ideal networks are not optimized or buffered during synthesis. Ideal clocking is highly optimistic. To get more accurate timing results, you can specify nonzero latency, uncertainty, and transition times for clock signals to represent the approximate timing values expected for the completed clock network. For example,
dc_shell> set_clock_latency 1.2 -rise [get_clocks CLK1]
dc_shell> set_clock_latency 0.9 -fall [get_clocks CLK1]
dc_shell> set_clock_uncertainty -setup 0.65 [get_clocks CLK1]
dc_shell> set_clock_uncertainty -hold 0.45 [get_clocks CLK1]
dc_shell> set_clock_transition 0.34 -rise [get_clocks CLK1]
dc_shell> set_clock_transition 0.30 -fall [get_clocks CLK1]
通過這樣的設置，時鍾網絡仍然被認為是理想的，但是在整個時鍾網絡中指定的延遲，不確定性和偏斜值而不是零。 除時鍾以外的高扇出網絡（例如復位或啟用信號）可能還需要在布局階段而不是在Design Compiler中合成的緩沖樹。 對於這些網絡，可以在布局工具中預期高扇出網絡綜合的情況下，指定理想的網絡行為以及非零延遲和過渡時間以進行綜合。 例如，
dc_shell> set_ideal_network [get_ports Reset]
dc_shell> set_ideal_latency 1.40 [get_ports Reset]
dc_shell> set_ideal_transition 0.30 [get_ports Reset]
線負載模型與拓撲技術
Wire Load Models and Topographical Technology
為了執行准確的時序分析，必須知道信元延遲和凈延遲。但是，在預布局邏輯綜合階段，由於導線長度未知，因此無法確定確切的凈延遲。您可以使用兩種方法來估計Design Compiler中的RC導線特性：導線負載模型和地形技術。線負載模型會根據網絡的扇出，為每個網絡獲得一個寄生電阻值和一個電容值。扇出較大的網絡被假定具有更多的導線，因此具有更多的電阻和電容。線負載模型在技術庫中提供。這些模型基於從相似設計中提取的數據，這些數據采用相同的工藝技術制造，尺寸相似。一個庫通常具有多個線負載模型，以用於不同的設計尺寸。隨着設計尺寸的增加，標准單元可以在該設計中物理上分開放置，這意味着導線長度通常會更長。一些庫供應商可能會在其模型中使用名稱來表示不同的設計尺寸，例如" 300kGates"，" 600kGates"等等。根據尺寸為設計選擇合適的線負載模型很重要。例如，
To perform accurate timing analysis, both cell delays and net delays must be known. However, at the prelayout logic synthesis stage, the exact net delays cannot be determined because the wire lengths are unknown. There are two methods you can use to estimate the RC wire characteristics in Design Compiler: wire load models and topographical technology. A wire load model obtains one parasitic resistance value and one capacitance value for each net, based on the net's fanout. A net having a larger fanout is assumed to have more wires and therefore more resistance and capacitance. Wire load models are supplied in the technology library. The models are based on data extracted from similar designs for similar size, fabricated with the same process technology. A library typically has several wire load models to be used for different design sizes. As the size of a design increases, standard cells can be placed physically farther apart within that design, which means that wire lengths are typically longer. Some library vendors may use names for their models to represent different design sizes, such as "300kGates,"600kGates," and so on. It is important to select the appropriate wire load model for the design according to size. For example,
dc_shell> set_wire_load_model -name 1.6MGates
指定的模型適用於當前設計級別及以下的所有網絡。 當設計是分層的並且模塊被分組到芯片的物理區域時，較小的單個線負載模型可以更好地表示每個較低級別子設計中的實際RC值。 例如，
The specified model applies to all nets at the current design level and below. When the design is hierarchical and the blocks are grouped into physical areas of the chip, then smaller individual wire load models can better represent the actual RC values within each lower-level subdesign. For example,
dc_shell> set_wire_load_model -name 1.6MGates
dc_shell> set_wire_load_mode enclosed
dc_shell> set_wire_load_model -name 800KGates [get_designs SUB1]
dc_shell> set_wire_load_model -name 200KGates [get_designs B1]
dc_shell> set_wire_load_model -name 100KGates [get_designs B2]
將線負載模式設置為"封閉"意味着，使用在完全包圍該網的最小子設計上設置的線負載模型來計算每個網的線電容。 一些庫支持基於設計區域的自動線負載選擇。可以通過auto_wire_load_selection變量控制此功能的使用。 線負載模型基於統計平均值，並不特定於特定設計。 在超深亞微米設計中，由於導線寄生物對路徑延遲的影響增加，導線負載模型可能無法提供足夠的精度。 對於這些設計，建議使用具有拓撲分析技術的Design Compiler。
Setting the wire load mode to "enclosed" means that the wire capacitance of each net iscalculated using the wire load model set on the smallest subdesign that completely encloses that net. Some libraries support automatic wire load selection based on the area of the design.
Usage of this feature can be controlled with the auto_wire_load_selection variable. Wire load models are based on statistical averages and are not specific to the particular design. In ultra-deep submicron designs, wire load models may not provide enough accuracy because of the increased impact of wire parasitics on path delays. For these designs, Design Compiler with topographical technology is recommended.
采用拓撲技術的Design Compiler無需使用線負載模型即可准確地預測合成過程中的時序。 取而代之的是，它使用來自Milkyway數據庫的物理信息來准確預測實際導線長度，並獲得對實際導線電阻和電容值的更准確預測。 它使用設計平面圖（如果可用），或者創建自己的平面圖（如果需要），以獲取預測導線長度所需的布局信息。 地形模式需要DC Ultra和DesignWare許可證。要在拓撲分析模式下運行Design Compiler，請在調用dc_shell時使用-topographical選項：
Design Compiler with topographical technology accurately predicts timing during synthesis without using wire load models. Instead, it uses physical information from the Milkyway database to accurately predict actual wire lengths and obtain more accurate predictions of actual wire resistance and capacitance values. It uses the design floorplan if available, or it creates its own floorplan if needed, to get the placement information it needs for predicting wire lengths. The topographical mode requires DC Ultra and DesignWare licenses.
To run Design Compiler in topographical mode, use the -topographical option when you invoke dc_shell:
% dc_shell -topographical
...
Initializing...
Starting shell in Topographical mode...
...
dc_shell-topo>
在拓撲分析模式下，shell提示符為dc_shell-topo>，此時無需線負載模型； 如果存在線負載模型，則將其忽略。 當您運行compile_ultra命令時，它會自動調用拓撲分析特征。 該命令在后台執行放置以准確估計導線長度。 單元放置基於DEF格式提供的現有平面布置圖，或者是使用諸如asset_placement_area，set_port_location，set_cell_location和create_placement_bounds等命令手動指定的布置圖。
The shell prompt is dc_shell-topo> in topographical mode. No wire load models are needed; if any are present, they are ignored. When you run the compile_ultra command, it automatically invokes the topographical features. The command performs placement in the background to estimate wire lengths accurately. Cell placement based is on an existing floorplan provided in DEF format or a floorplan specified manually with commands such asset_placement_area, set_port_location, set_cell_location, and create_placement_bounds.
物理Milkyway參考庫包含綜合網表中單元的物理布局描述，包括標准單元，宏單元和填充單元，Design Compiler在編譯操作期間將其用於地形布局。 技術文件定義了過程金屬層，物理設計規則，電阻，電容單位等。 TLUPlus文件定義了用於從提取的導線數據中計算超深亞微米RC寄生值的模型。DesignCompiler使用此物理信息獲得了一個放置模型，該模型可以准確地預測導線的長度，從而准確地預測導線的RC和延遲特性。 結果是在邏輯綜合和物理實現之間實現了更高質量的綜合和更少的設計迭代。
The physical Milkyway reference libraries contain the physical layout descriptions of the cells in the synthesized netlist, including standard cells, macro cells, and pad cells, which Design Compiler uses for topographical placement during compile operations. The technology file defines the process metal layers, physical design rules, units of resistance, capacitance, and so on. The TLUPlus files define models for calculating ultra-deep-submicron RC parasitic values from extracted wire data.By using this physical information, Design Compiler obtains a placement model that accurately predicts wire lengths and therefore wire RC and delay characteristics. The result is a higher-quality synthesis and fewer design iterations between logic synthesis and physical implementation.
設計划分
Design Partitioning
大型設計通常分為多個塊層次，通常按功能進行組織，以將設計和實現任務分解為可管理的單元。 為了獲得最佳結果，對設計進行分區非常重要，這樣可以使Design Compiler優化每個塊邊界內的時序和面積。 例如，考慮圖1-17所示的邏輯分區。 寄存器A和寄存器B之間的組合邏輯已在模塊A和模塊B之間進行了划分。一些"膠合邏輯"（一個反相器）將邏輯匯總在一起。 設計編譯器必須保留模塊A和模塊B的引腳定義，因此它不能跨它們之間的層次邊界執行邏輯優化。 此外，沒有機會優化頂層的反相器。
A large design is typically divided into a hierarchy of blocks, often organized by function, to break down the design and implementation task into manageable units. To get the best possible results, it is important to partition the design in a manner that allows Design Compiler to optimize the timing and area within the boundaries of each block. For example, consider the partitioning of logic shown in Figure 1-17. The combinational logic between Register A and Register B has been divided between Block A and Block B. Some "glue logic," an inverter, holds the logic together at the top level. Design Compiler must preserve the Block A and Block B pin definitions, so it cannot perform logic optimization across the hierarchical boundary between them. Furthermore, there is no opportunity to optimize away the inverter at the top level.
圖1-17 較差的模塊划分
Figure 1-17 Poorly Partitioned Blocks
圖1-18所示的邏輯分區要好得多。 寄存器A和寄存器B之間的組合邏輯已完全移入了塊B，包括頂層"膠粘邏輯"。 這種划分允許DC一起優化塊B內的所有邏輯，這可能會導致組合邏輯的該部分的時間延遲更短，面積更小或兩者兼而有之。 分區是在寄存器A的輸出而不是寄存器B的輸入處進行的，從而使設計編譯器有機會通過使用更復雜的觸發器單元來進一步優化邏輯。 例如，可以通過使用使能型觸發器來實現邏輯中的復用功能。
The logic partitioning shown in Figure 1-18 is much better. The combinational logic between Register A and Register B has been moved entirely into Block B, including the top-level "glue logic." This partitioning allows Design Compiler to optimize all of the logic together inside block B, possibly resulting in less time delay, smaller area, or both for that portion of the combinational logic. The partition was made at the output of Register A, not at the input of Register B, to give Design Compiler an opportunity to further optimize the logic by using a more complex flip-flop cell. For example, a multiplexing function in the logic could be implemented by using an enable-type flip-flop.
圖1-18 良好的設計划分
Figure 1-18 Well-Partitioned Blocks
為了獲得更好的結果，請避免在不同的塊之間划分組合邏輯。 取而代之的是，將盡可能多的組合邏輯保持在一起，並將其與下游寄存器（如上述示例中的寄存器B）保持在一起。 必要時，在寄存器的輸出（例如上述示例中的寄存器A的輸出）進行分區。 這簡化了低級塊綜合的輸入和輸出時序約束的設置，並為Design Compiler提供了近一個完整的時鍾周期，可在其中優化寄存器到寄存器的邏輯。
在原始RTL中執行良好的分區是最佳策略。 但是，如果RTL分區不合適，則可以在編譯操作之前通過取消邏輯分組並將邏輯重新分組為更有利的配置來改進Design Compiler中的分區。 默認情況下，compile_ultra命令執行自動重新分區。 您也可以使用ungroup和group命令手動重新划分設計。
For better results, avoid dividing combinational logic between different blocks. Instead, keep as much combinational logic together and keep it with the downstream registers, such as Register B in the foregoing example. Where necessary, make a partition at the output of a register, such as the output of Register A in the foregoing example. This simplifies the setting of input and output timing constraints for lower-level block synthesis and provides Design Compiler with nearly a whole clock cycle in which to optimize the register-to-register logic.
Performing good partitioning in the original RTL is the best strategy. However, if the RTL partitioning is not favorable, you can improve the partitioning in Design Compiler by ungrouping and regrouping the logic into a more favorable configuration prior to the compile operation. The compile_ultra command, by default, performs automatic repartitioning. You can also manually repartition the design with the ungroup and group commands.
路徑分組
Path Groups
設計的時序路徑被組織為稱為路徑組的組（不要與上一節中描述的邏輯組混淆）。 默認情況下，設計中的每個時鍾都有一個路徑組。 給定時鍾在該路徑上計時的所有時序路徑
端點屬於該時鍾的路徑組。 一個只有一個時鍾的設計只有一個時鍾路徑組，因此設計中的所有時鍾路徑都屬於該組。 路徑組中的所有時序路徑均經過優化，可以一起從關鍵點開始時序
路徑，這是組內松弛最嚴重的路徑。 關鍵路徑修復后，下一條最差路徑將成為新的關鍵路徑和修復目標。 該工具將繼續固定路徑，直到組中的所有路徑的零松弛或直到更好的優化為止
找不到當前關鍵路徑的解決方案。 在后一種情況下，次臨界路徑不是固定的，但會留下時序違規。
The timing paths of the design are organized into groups called path groups (not to beconfused with logic grouping described in the foregoing section). By default, there is onepath group for each clock in the design. All timing paths clocked by a given clock at the path
endpoint belong to that clock's path group. A design that has only a single clock has only oneclocked path group, so all clocked paths in the design belong to that group. All timing paths within a path group are optimized for timing together, starting with the critical
path, which is the path having the worst slack within the group. After the critical path is fixed, the next-worst path becomes the new critical path and the target for fixing. The tool continues fixing paths until all paths in the group have zero slack or until a better optimization
solution for the current critical path cannot be found. In the latter case, the subcritical paths are not fixed, but are left with timing violations.
次臨界路徑是比臨界路徑具有更好松弛度的路徑，但是仍然違反。 優化組中的路徑並與其他組分開報告。 例如，在具有兩個時鍾CLK1和CLK2的設計中，有兩個路徑組。 設計編譯器從最關鍵的路徑開始，依次優化每個路徑組，即使兩個組之間的最差松弛時間不同。
您可以選擇將路徑分為幾組，以控制優化工作集中在目標路徑上。 例如，如果不確定輸入延遲要求，則可以將輸入到注冊路徑放入單獨的組中。 在這種情況下，輸入到寄存器路徑與其他路徑分開優化，最壞的輸入到寄存器沖突並不能阻止對同一時鍾提供時鍾的寄存器到寄存器路徑的優化。 分組路徑的命令是group_path。 例如，
The subcritical paths are the paths with better slack than the critical path, but that are still in violation. Paths within a group are optimized and reported separately from other groups. For example, in a design with two clocks, CLK1 and CLK2, there are two path groups. Design Compiler
optimizes each path group in turn, starting with the critical path in each group, even if the worst slacks are different between the two groups.
You can optionally divide the paths into groups to control the focus of optimization effort on targeted paths. For example, if you are not sure about the input delay requirements, you can put the input-to-register paths into a separate group. In that case, the input-to-register paths
are optimized separately from the other paths and the worst input-to-register violation does not prevent optimization of register-to-register paths clocked by the same clock. The command for grouping paths is group_path. For example,
dc_shell> create_clock -name CLK -period 1.67 [get_ports CLK]
dc_shell> group_path -name INREG -from [all_inputs]
dc_shell> group_path -name REGOUT -to [all_outputs]
dc_shell> group_path -name INOUT -from [all_inputs] -to [all_outputs]
默認情況下，由CLK計時的路徑在路徑端點的所有路徑都屬於CLK路徑組。 在此示例中，三個group_path命令將輸入到寄存器路徑，寄存器到輸出路徑和輸入到輸出路徑分別放置在分別稱為INREG，REGOUT和INOUT的單獨路徑組中。 寄存器間路徑保留在默認的CLK組中，如圖1-19所示。
By default, all paths clocked by CLK at the path endpoint belong to the CLK path group. In this example, the three group_path commands place the input-to-register, register-to-output, and input-to-output paths into separate path groups called INREG, REGOUT, and INOUT, respectively. The register-to-register paths remain in the default CLK group as demonstrated in Figure 1-19.
圖1-19 時序路徑分組
Figure 1-19 Timing Path Groups
使用此路徑分組，在優化與輸入相關或與輸出相關的時序路徑時遇到的任何問題都不會影響寄存器到寄存器路徑的優化。 此外，report_timing命令報告每個路徑組中的最差路徑因此，您可以分別從輸入相關路徑和輸出相關路徑中找出最差的寄存器到寄存器路徑。
With this path grouping, any problems encountered in optimizing input-related or output-related timing paths will not affect the optimization of register-to-register paths. Furthermore, the report_timing command reports the worst path in each path group
separately, so you can find out about the worst register-to-register paths separately from the input-related and output-related paths.
您可以選擇為每個路徑組分配一個權重，也稱為成本函數，以便Design Compiler花費更多的精力來優化目標組。 每個路徑組的默認權重值為1。權重越高，應用於該組的工作量就越大。 例如，以下命令與前面的示例一樣分配與輸入有關的路徑和與輸出有關的路徑，但也將工作量級別指定為寄存器到寄存器路徑5和2到輸入到寄存器路徑。 對於其他類型的路徑，工作量級別保持為1。
You can optionally assign a weight, also known as cost function, to each path group so that Design Compiler applies more effort to optimizing the targeted group. The default weighting value for each path group is 1. The higher the weighting, the higher the effort applied to the group. For example, the following commands assign the input-related and output-related paths as in the previous example, but also specify an effort level of 5 for the register-to-register paths and 2 to the input-to-register paths. The effort level remains at 1 for the other types of paths.
dc_shell> create_clock -name CLK -period 1.67 [get_ports CLK]
dc_shell> group_path -name INREG -from [all_inputs] -weight 2
dc_shell> group_path -name REGOUT -to [all_outputs]
dc_shell> group_path -name INOUT -from [all_inputs] -to [all_outputs]
dc_shell> group_path -name CLK -weight 5
一個組若擁有較高的權重意味着Design Compiler將嘗試減少該組中路徑的時序違規的大小，但代價是屬於較低權重組的路徑的松弛。 要獲取有關當前路徑組集的信息，請使用report_path_group命令。 要刪除路徑組，請使用remove_path_group命令。 屬於已刪除組的路徑被隱式分配給默認路徑組。
Higher weighting for a group means that Design Compiler will attempt to reduce the size of a timing violation for a path in that group at the expense of slack in a path belonging to a lower-weighted group. To get information about the current set of path groups, use the report_path_groupcommand. To remove a path group, use the remove_path_group command. Paths belonging to a removed group are implicitly assigned to the default path group.
寄存器時序再優化
Register Retiming Optimization
滿足時序約束的另一種方法是在組合邏輯內重新放置寄存器。 例如，在圖1-20中，由於較長的組合邏輯路徑，左側的時序路徑違反了設置時序，該路徑的總時間裕量為–1.0。 同時，下游的短時間路徑擁有一個+1.5的時間裕量。
Another way to meet timing constraints is to reposition registers within the combinational logic. For example, in Figure 1-20, the timing path on the left has a setup timing violation due to a long combinational logic path, with a total slack of –1.0 for the path. Meanwhile, the short timing path downstream has a positive slack of +1.5.
圖1-20 建立時間違例
Figure 1-20 Setup Timing Violation
Design Compiler可以通過更改實現來解決此沖突，如圖1-21所示。 它會取走"與非"門輸出處的寄存器，並用同一"與非"門的輸入處的兩個新寄存器代替它。 這產生了一個邏輯上等效的電路，該電路通過了兩條路徑的建立時序。 該改變有效地消除了來自違反路徑的NAND門的延遲，並將該延遲提供給下游路徑。 這種定時違規校正的成本是電路中附加寄存器的面積。
Design Compiler can fix this violation by changing the implementation as shown inFigure 1-21. It takes away the register at the output of the NAND gate and replaces it with two new registers at the inputs of the same NAND gate. This produces a logically equivalent circuit that passes setup timing for both paths. The change effectively takes away the delay of the NAND gate from the violating path and gives that delay to the downstream path. The cost of this timing violation correction is the area of the additional register in the circuit.
圖1-21 通過寄存器時序調整修復違例
Figure 1-21 Violation Fixed by Register Retiming
相反，如圖1-21所示的電路，但在第一時序路徑中有一些可用的時序裕量，可以通過取下與非門輸入處的兩個寄存器並用一個代替單個寄存器來減小總面積。 在與非門的輸出處注冊。通過拆分或合並寄存器並通過組合邏輯移動這些寄存器（無論是為了獲得更好的時序還是達到更好的面積）而進行的優化稱為寄存器重新定位或寄存器重新計時。 這種類型的優化是通過命令compile_ultra -retime，balance_registers或optimize_registers執行的。
Conversely, a circuit like the one shown in Figure 1-21, but with some available timing slack in the first timing path, can reduce the total area by taking away the two registers at the inputs of the NAND gate and replacing them with a single register at the output of the NAND gate.
Optimization performed by splitting or merging registers and moving those registers through combinational logic, whether for better timing or better area, is called register repositioningor register retiming. This type of optimization is performed with the commandcompile_ultra -retime, balance_registers, or optimize_registers.