Introduction to Synthesis Timing（1）
RTL綜合時序介紹（1）
Static timing analysis is a method of validating the timing performance of a design bychecking all possible paths for timing violations under worst-case conditions. It considers the worst possible delay through each logic element, but not the logical operation of the circuit.
靜態時序分析是一種通過檢查在最壞情況下所有可能存在時序違例的路徑來驗證設計的時序性能的方法。它考慮了每個邏輯單元的最差延遲，而不是考慮電路的邏輯操作。
In comparison to circuit simulation, static timing analysis is faster and more thorough. It is faster because it does not need to simulate multiple test vectors.
相對於電路仿真而言，靜態時序分析更快也更深入。因為它不需要模擬多個仿真向量，所以它更快。
It is more thorough because it checks the worst-case timing for all possible logic conditions, not just those sensitized by a particular set of test vectors.
它更深入，因為它檢查了在所有可能得邏輯情況下的最差時間，而不是只對特定的一組測試向量敏感。
However, static timing analysis checks the design only for proper timing, not for correct logical functionality. Timing, area, and power constraints drive the operation of synthesis with Design Compiler and physical implementation with IC Compiler.
然而，靜態時序分析只檢查設計設計是否擁有合適的時序，而不會檢查設計的邏輯正確性。時序，面積，功耗約束驅動着DC的綜合操作與ICC的物理實現。
These tools synthesize the netlist and perform physical placement and routing with the goal of making the fastest device, using the least area and power, in the shortest turn around time that is consistent with the designrequirements.
這些工具綜合了網表，並執行物理布局和布線，在最短的翻轉時間內使用最少的面積和功耗，實現最快器件的目標，盡可能實現與設計目標一致的結果
These tools perform trade-offs between speed, area, power, and runtime according to the constraints set by the designer. However, a chip must meet the timing constraints to operate at the intended clock rate, so timing is the most important designconstraint.
這些工具需要根據設計者設置的約束在速度，面積，功耗，運行時間之間做出權衡取舍。然而，一塊芯片必須要滿足在預定時鍾頻率下的時序約束，所以時序是最重要的設計約束。
Static timing analysis seeks to answer the question, "Will the correct data be present at the data input of each synchronous device when the clock edge arrives, under all possible conditions?"
靜態時序分析看起來是要在尋找這個問題的答案，即：在所有可能的情況下，當時鍾沿到達時，正確的數據是否會及時出現在每個同步器件的數據出入端？
Figure 1-1 TIMING PATH
the dashed arrow represents a timing path. The change in signal data caused by a clock transition at flip-flop FF1 must be propagated to flip-flop FF2 before the following clock edge arrives at FF2, so that the logically processed data can be reliably latched into FF2. The change at FF1.Q might affect the output of the combinational logic cloud at FF2.D, depending on the logic itself, the data value, and the values of any side inputs feeding into the logic. The change at FF2.D, if any, must occur before the next clock edge arriving at FF2.
虛線箭頭表示了一個時間路徑，由於觸發器FF1中的時鍾轉換導致的信號數據的改變必須在FF2的時鍾上升沿之前到達，使得這個經過邏輯處理的數據可以被可靠的鎖存進FF2。FF1_Q端的變化可能影響到在FF2_D端的組合邏輯塊的輸出，這取決於邏輯塊的本身，數據的值，以及任何輸入進邏輯塊的值。FF2_D端的變化必須發生在FF2時鍾邊沿到達之前。
Figure 1-2 Setup Check Timing
Figure 1-2 shows the timing for this path. The arrival of a clock edge at FF1 latches the data at the input FF1.D into the flip-flop. It also places that data on the flip-flop output, FF1.Q，after the clock-to-Q delay of the flip-flop. This is called the launch event for the timing path。
圖1-2顯示了這條路徑的時序。當時鍾邊緣到達FF1時，FF1鎖存FF1.D端的數據進入觸發器。在經過觸發器CLK to Q的延時過后，數據將放置在FF1.Q端。這個過程稱為這條時鍾路徑的啟動事件。
This signal goes through the combinational logic with some delay. The output of the
combinational logic is at the input of the second flip-flop, FF2.D. The time at which the signal value changes here is called the arrival time for the path.
這個信號穿過組合邏輯時會經過一些延時。組合邏輯的輸出是第二個觸發器FF2.D的輸入。這里信號值變化的時間稱為路徑到達時間。
The change in value at FF2.D must occur before the arrival of the clock edge arriving at FF2，by at least an amount equal to the setup time requirement for the flip-flop. This latest allowable arrival time is called the required time for the path. The latching of data at FF2 is called the capture event for the timing path. In this example, the capture event occurs one whole clock cycle after the launch event.
FF2.D值變化必須在時鍾邊緣到達FF2之前發生，其發生時間至少等於觸發器所需的建立時間。這個最小的允許到達時間稱為路徑的必需時間。FF2上的數據鎖存稱為時間路徑的捕獲事件。在本例中，捕獲事件在啟動事件之后的整個時鍾周期內發生。`
The amount of time by which the timing constraint is met is called the slack of the timing check. If the signal arrives earlier than necessary as shown in Figure 1-2, the slack is positive. If the signal arrives exactly at the required time, the slack is zero and the timing constraint is barely met. If the signal arrives later than the required time, the slack is negative.
In all three cases, the amount of slack is the required time minus the arrival time.For example, if the required time is 1.8 ns after the launch clock edge and the arrival time is 1.6 ns after the launch clock edge, the slack is 1.8 minus 1.6, or 0.2 ns, a positive number.
滿足時序約束的時間量稱為時序檢查的裕量。如圖1-2所示，若信號提前到達，則裕量為正。如果信號恰好在要求的時間到達，則裕量為零，剛好滿足時序約束。如果信號到達的比要求的滿，那么裕量為負。在所有的三種情況中，裕量的大小等於所要求的時間減去實際到達的時間。比如在時鍾沿觸發后的要求時間為1.8ns，實際到達時間為時鍾沿觸發后1.6ns，那么時間裕量為0.2ns，為一個正值。
The preceding timing check is called a setup check, which verifies that a change in data arrives soon enough before each clock edge at the sequential device. This is the most common type of timing check that drives synthesis and optimization.
前面所述的時序檢查稱為建立（時間）檢查，它驗證數據的變化是否在時序設備的每個時鍾邊緣之前能夠及時到達。這是用於綜合和優化的最常見的時序檢查類型。
However, other types of timing checks can be performed as well. For example, a hold check verifies that the data remains valid during and after the arrival of the clock edge at the end of the path by a sufficient amount.
A hold violation can occur if the shortest possible combinational delay from launch to capture is very short and the longest delay from the launch clock edge to the capture clock edge is very long. An example is shown in Figure 1-3 and Figure 1-4.
然而，還有一些其他類型的時序檢查也需要執行。舉例來說，一個保持（時間）檢查驗證在時間沿達到以及達到末端路徑之后，數據是否保持一個足夠的時間。當發射到捕獲的最短可能的組合延遲非常短時，而從發射時鍾到捕獲時鍾的最長延遲非常長時，可能會發生保持時間違例。
如圖1-3和圖1-4所示。
Figure 1-3 Hold Check Timing Path Example
In Figure 1-3, the timing path has a very short combinational delay from FF1 to FF2,
consisting of a single NAND gate. Meanwhile, there is a long delay for the clock signal between the two flip-flops because of the three buffers, possibly made even longer by a large RC delay due to a long route. Therefore, the capture clock signal CLK2 arriving at FF2 is significantly delayed with respect to the launch clock CLK1 at FF1.
如圖1-3所示，FF1到FF2的時序路徑之間存在着很短的組合邏輯延遲，僅僅是一個與非門。同時，由於時鍾路徑上存在3個緩沖器，在兩個觸發器之間存在着一個很長的延時，甚至由於長路徑導致的大的RC延遲，兩者之間的延遲可能還會變的更大。
因此，捕獲時鍾信號CLK2到達FF2時顯著落后於CLK1達到FF1的時間點。
Figure 1-4 Hold Check Timing
Figure 1-4 shows the possible timing in this situation. The setup constraint is met easily because the data arrives well before the required setup time. However, the hold constraint is not met because the data at the D input of FF2 is not held long enough after the nominal clock arrival time.
圖1-4顯示了這種情況下可能的時序。建立時間約束更容易滿足，因為數據在需求的建立時間之前已經達到了。然而，保持時間約束不那么好滿足，因為FF2輸入端D上的數據輸入在標准達到時間之后沒有保持足夠長的時間。
The data changes before the delayed clock CLK2 has a chance to latch it in. This type of violation can be fixed by shortening the delay in the clock line or by increasing the delay in the data path.
數據在已被延遲的時鍾CLK2能夠鎖存他之前已經改變了。這種違例可以通過減少時鍾線上的延遲或者通過增加數據通路上的延遲進行解決。
By default, the synthesis or implementation tool fixes setup violations, but not hold violations,because setup requirements are more difficult to satisfy.
默認情況下，綜合或實現工具可以修復建立時間問題，但保持違例更難修復。
To have the tool fix hold violations as well as setup violations, use the set_fix_hold command.
如需工具在修復保持時間違例的同時修復建立時間違例，使用set_fix_hold命令
This command sets the fix_hold attribute on specified clocks, which directs the tool to check for and fix hold violations during the compile operation.
這個命令給特定的模塊設定了fix_hold屬性，該屬性告訴工具在編譯操作期間檢查並修復保持時間違例。
Each type of timing check considers different worst-case conditions. For example, a setup check considers the longest and slowest possible path through the combinational logic of the data path and the earliest possible arrival of the capture clock edge with respect to the launch clock edge.
每種類型的時序檢查考慮不同的最壞情況。舉例來說，一個建立時間檢查需要考慮通過組合邏輯的數據通路中最長和最短的可能路徑，以及相對於發射時鍾沿，捕獲時鍾沿最早可能到達的路徑。
Conversely, a hold check considers the shortest and fastest possible path through the combinational logic of the data path and the latest possible arrival of the capture clock edge with respect to the launch clock edge.
相反的，一個保持時間檢查需要考慮最短和最快的通過組合邏輯的可能的數據路徑，以及相對於發射時鍾沿最慢的捕獲時鍾沿的路徑。
Figure 1-5 shows examples of different pathways that can be taken through the same block of combinational logic. In a data path, a setup check would consider the longer delay through three gates, whereas a hold check would consider the shorter path through two gates.
圖1-5 顯示了通過同樣一個組合邏輯塊不同的路徑。在一個數據路徑中，建立時間檢查需要考慮通過三個門的更長的延時，而保持時間檢查將考慮通過兩個門的更短的延時。
A synthesis, optimization, or analysis tool can perform timing checks on the following types of paths:
一個綜合、優化或者分析工具可以對以下種類的路徑執行時序檢查：
• Clock path (a path from a clock input port or cell pin, through one or more buffers or inverters, to the clock pin of a sequential element) for data setup and hold checks
時鍾路徑（從時鍾輸入端口或單元管腳，通過一個或多個緩沖器或反相器，到時序元件的時鍾管腳的一種路徑）
• Clock-gating path (a path from an input port to a clock-gating element) for clock-gating setup and hold checks
•時鍾門控路徑(從輸入端口到時鍾門控單元的路徑)，用於設置時鍾門控並進行檢查
• Asynchronous path (a path from an input port to an asynchronous set or clear pin of a sequential element) for recovery and removal checks
用於恢復和清除檢查的異步路徑(從輸入端口到時序單元的異步置位或清除引腳的路徑)
• Data-to-data check (a custom timing check specified with the set_data_check command, having specified setup and hold times between data signals)
數據到數據路徑檢查(使用set_data_check命令指定的自定義時序檢查，指定了數據信號之間的建立和保持時間)
Some of these path types are shown in Figure 1-6
Figure 1-6 Path Types
A tool can also perform timing checks on the asynchronous preset and clear inputs of sequential devices. A recovery check verifies that enough time has passed after the inactivation of an asynchronous control signal before a clock edge occurs.
工具還可以對輸入時序單元的異步預置和清除信號執行時序檢查。恢復檢查驗證在時鍾沿到來之前，離異步控制信號失效已經經過了足夠長的時間。
A removal check verifies that enough time has passed after a clock edge before the removal of an asynchronous control signal. These types of checking are enabled by setting the enable_recovery_removal_arcs variable to true.
清除檢查會驗證，在異步控制信號移除之前，離時鍾沿已經經過了足夠長的時間。
A clock-gating check is a setup or hold check performed on the control input of a clock-gating cell. This type of check detects occurrences of clipped clocked edges or spurious clock pulses. The command for specifying clock-gating checks is set_clock_gating_check.
時鍾門控檢查是一種對時鍾門控單元的控制輸入的建立時間和保持時間的檢查。這種類型的檢查檢測削峰的時鍾邊沿或者虛假的時鍾脈沖。這個用於指定時鍾門控檢查的命令是set_clock_gating_check