詳解zynq/zynqmp的gpio系統

zynq7000系列擁有共計最多118個gpio的引腳控制（理論上ps+pl）,其中MIO 54個，EMIO64個，其trm的框圖如下

zynqmp系列同樣如下 其MIO 78 EMIO 96 其trm的框圖如下

此外zynq還可以通過AXI總線進行GPIO的擴展
在vivado的框圖上如下所示，這里用的是7020 的器件，zynqmp與其相似

接下來詳細敘述 如何使用

這里還是以7020為例，zynqmp與其極其相似 就是位號稍有差異而已

1)首先是最簡單的，在內核起來后如何使用

這個直接在sys文件系統的gpio下即可使用，我這邊使用AXI_GPIO擴展了三組gpio，其中的兩組在內核下使能了，所以gpio下可以看到三個chip組

進一步可以看到903為起始的標號對應的為MIO+EMIO的gpio

其他兩個為AXI擴展的

例如：

這里面如果想使用MIO28則直接以903+28的位號導出gpio就可以，（sys下如何使用gpio，自己學一下，只是使用的網上很多）

如果使用EMIO10的話則導出的位號為903+54+10（54位MIO的個數）

如果使用41200000對應的axi_gpio[1]的話則導出的位號為1023(1022+1)（AXI的地址在vivado中可以看到）

2)如果在內核驅動中使用gpio節點該怎么做

這里面主要通過dts向內核中傳遞，使用如下的格式進行

其中axi的節點說明在pl.dtsi中可以看到，包括基址，位寬，默認值，等
3)
在uboot中使用

在uboot下使用的常用場景為對某一器件進行rest

這里直接貼出代碼modify from zynq_gpio.c and xilinx_gpio.c

下面是適用於MIO/EMIO的代碼

#define ZYNQ_GPIO_MAX_BANK 4
#define ZYNQMP_GPIO_MAX_BANK 6
#define ZYNQ_GPIO_BANK0_NGPIO 32
#define ZYNQ_GPIO_BANK1_NGPIO 22
#define ZYNQ_GPIO_BANK2_NGPIO 32
#define ZYNQ_GPIO_BANK3_NGPIO 32
 
#define ZYNQMP_GPIO_NR_GPIOS    174
#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
                            ZYNQ_GPIO_BANK1_NGPIO + \
                            ZYNQ_GPIO_BANK2_NGPIO + \
                            ZYNQ_GPIO_BANK3_NGPIO)
 
struct zynq_platform_data
{
    const char *label;
    u16 ngpio;
    u32 max_bank;
    u32 bank_min[ZYNQMP_GPIO_MAX_BANK];
    u32 bank_max[ZYNQMP_GPIO_MAX_BANK];
};
 
#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
                                      ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
                                      ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
                                      ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
                                      ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
 
static const struct zynq_platform_data zynq_gpio_def = {
    .label = "zynq_gpio",
    .ngpio = ZYNQ_GPIO_NR_GPIOS,
    .max_bank = ZYNQ_GPIO_MAX_BANK,
    .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
    .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
    .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
    .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
    .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
    .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
    .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
    .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
};
 
static const struct zynq_platform_data zynqmp_gpio_def = {
    .label = "zynqmp_gpio",
    .ngpio = ZYNQMP_GPIO_NR_GPIOS,
    .max_bank = ZYNQMP_GPIO_MAX_BANK,
    .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
    .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
    .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
    .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
    .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
    .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
    .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
    .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
    .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
    .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
    .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
    .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
};
/**
 * @brief copy from zynq_gpio.c
 *
 */
 
#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
/* MSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
/* Data Register-RW */
#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
/* Direction mode reg-RW */
#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
/* Output enable reg-RW */
#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
/* Interrupt mask reg-RO */
#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
/* Interrupt enable reg-WO */
#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
/* Interrupt disable reg-WO */
#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
/* Interrupt status reg-RO */
#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
/* Interrupt type reg-RW */
#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
/* Interrupt polarity reg-RW */
#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
/* Interrupt on any, reg-RW */
#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
/* Mid pin number of a bank */
#define ZYNQ_GPIO_MID_PIN_NUM 16
/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
/**
 * @brief copy and modify from zynq_gpio.c
 *
 * @param pin_num
 * @param bank_num
 * @param bank_pin_num
 */
void zynq_gpio_get_bank_pin(unsigned int pin_num, unsigned int *bank_num, unsigned int *bank_pin_num)
{
    u32 bank;
 
    for (bank = 0; bank < zynq_gpio_def.max_bank; bank++)
    {
        if (pin_num >= zynq_gpio_def.bank_min[bank] &&
            pin_num <= zynq_gpio_def.bank_max[bank])
        {
            *bank_num = bank;
            *bank_pin_num = pin_num -
                            zynq_gpio_def.bank_min[bank];
            return;
        }
    }
 
    if (bank >= zynq_gpio_def.max_bank)
    {
        printf("Invalid bank and pin num\n");
        *bank_num = 0;
        *bank_pin_num = 0;
    }
}
 
#define ZYNQ_GPIO_BASEADDR 0xE000A000
 
static int zynq_gpio_direction_output(unsigned pin, int direction)
{
    u32 reg;
    unsigned int bank_num, bank_pin_num;
 
    zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
 
    /* set the GPIO pin as output */
    reg = readl(ZYNQ_GPIO_BASEADDR + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
    if (direction != (u32)0)
    { /*  Output Direction */
        reg |= ((u32)1 << (u32)bank_pin_num);
    }
    else
    { /* Input Direction */
        reg &= ~((u32)1 << (u32)bank_pin_num);
    }
    writel(reg, ZYNQ_GPIO_BASEADDR + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
    return 0;
}
 
static int zynq_gpio_enable_output(unsigned pin, int value)
{
    u32 reg;
    unsigned int bank_num, bank_pin_num;
 
    zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
 
    /* set the GPIO pin as output */
    reg = readl(ZYNQ_GPIO_BASEADDR + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
    if (value != (u32)0)
    { /*  Output Direction */
        reg |= ((u32)1 << (u32)bank_pin_num);
    }
    else
    { /* Input Direction */
        reg &= ~((u32)1 << (u32)bank_pin_num);
    }
    writel(reg, ZYNQ_GPIO_BASEADDR + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
    return 0;
}
 
static int zynq_gpio_set_value(unsigned pin, int value)
{
    unsigned int reg_offset, bank_num, bank_pin_num;
 
    zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
 
    if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM)
    {
        /* only 16 data bits in bit maskable reg */
        bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
        reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
    }
    else
    {
        reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
    }
 
    /*
     * get the 32 bit value to be written to the mask/data register where
     * the upper 16 bits is the mask and lower 16 bits is the data
     */
    value = !!value;
    value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
            ((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
 
    writel(value, ZYNQ_GPIO_BASEADDR + reg_offset);
 
    return 0;
}

在使用時采用如下的例子

eg:

zynq_gpio_direction_output(i, 1);//i的選擇與上述的dts下的選擇一致

zynq_gpio_enable_output(i , 1);

zynq_gpio_set_value(i, 0);

下面是適用於AXI_GPIO的代碼

#define XILINX_GPIO_MAX_BANK 2
 
/* Gpio simple map */
struct gpio_regs
{
    u32 gpiodata;
    u32 gpiodir;
};
 
struct xilinx_gpio_privdata
{
    u32 output_val[XILINX_GPIO_MAX_BANK];
};
 
struct xilinx_gpio_platdata
{
    struct gpio_regs *regs;
    int bank_max[XILINX_GPIO_MAX_BANK];
    int bank_input[XILINX_GPIO_MAX_BANK];
    int bank_output[XILINX_GPIO_MAX_BANK];
    u32 dout_default[XILINX_GPIO_MAX_BANK];
    struct xilinx_gpio_privdata priv;
};
struct xilinx_gpio_platdata axi_gpio_1;
struct xilinx_gpio_platdata axi_gpio_2;
 
static int xilinx_gpio_init()
{
    axi_gpio_1.regs = (struct gpio_regs *)0x41210000;
    axi_gpio_1.bank_max[0] = 2;
    axi_gpio_1.bank_input[0] = 0;
    axi_gpio_1.bank_output[0] = 0;
    axi_gpio_1.dout_default[0] = 0;
    axi_gpio_1.priv.output_val[0] = axi_gpio_1.dout_default[0];
 
}
 
static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
                                    u32 *bank_pin_num, struct xilinx_gpio_platdata *platdata)
{
    u32 bank, max_pins;
    /* the first gpio is 0 not 1 */
    u32 pin_num = offset;
 
    for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++)
    {
        max_pins = platdata->bank_max[bank];
        if (pin_num < max_pins)
        {
            debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
                  bank, pin_num);
            *bank_num = bank;
            *bank_pin_num = pin_num;
            return 0;
        }
        pin_num -= max_pins;
    }
 
    return -EINVAL;
}
 
static int xilinx_gpio_set_value(struct xilinx_gpio_platdata *platdata, unsigned offset,
                                 int value)
{
    struct xilinx_gpio_privdata *priv = &(platdata->priv);
    int val, ret;
    u32 bank, pin;
 
    ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, platdata);
    if (ret)
        return ret;
 
    val = priv->output_val[bank];
 
    debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
          __func__, (ulong)platdata->regs, value, offset, bank, pin, val);
 
    if (value)
        val = val | (1 << pin);
    else
        val = val & ~(1 << pin);
 
    writel(val, &platdata->regs->gpiodata + bank * 2);
 
    priv->output_val[bank] = val;
 
    return 0;
};
 
static int xilinx_gpio_get_value(struct xilinx_gpio_platdata *platdata, unsigned offset)
{
    struct xilinx_gpio_privdata *priv = &(platdata->priv);
    int val, ret;
    u32 bank, pin;
 
    ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, platdata);
    if (ret)
        return ret;
 
    debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
          (ulong)platdata->regs, offset, bank, pin);
 
    if (platdata->bank_output[bank])
    {
        debug("%s: Read saved output value\n", __func__);
        val = priv->output_val[bank];
    }
    else
    {
        debug("%s: Read input value from reg\n", __func__);
        val = readl(&platdata->regs->gpiodata + bank * 2);
    }
 
    val = !!(val & (1 << pin));
 
    return val;
};
 
static int xilinx_gpio_direction_output(struct xilinx_gpio_platdata *platdata, unsigned offset,
                                        int value)
{
    int val, ret;
    u32 bank, pin;
 
    ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, platdata);
    if (ret)
        return ret;
 
    /* can't change it if all is input by default */
    if (platdata->bank_input[bank])
        return -EINVAL;
 
    xilinx_gpio_set_value(platdata, offset, value);
 
    if (!platdata->bank_output[bank])
    {
        val = readl(&platdata->regs->gpiodir + bank * 2);
        val = val & ~(1 << pin);
        writel(val, &platdata->regs->gpiodir + bank * 2);
    }
 
    return 0;
}
 
static int xilinx_gpio_direction_input(struct xilinx_gpio_platdata *platdata, unsigned offset)
{
    int val, ret;
    u32 bank, pin;
 
    ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, platdata);
    if (ret)
        return ret;
 
    /* Already input */
    if (platdata->bank_input[bank])
        return 0;
 
    /* can't change it if all is output by default */
    if (platdata->bank_output[bank])
        return -EINVAL;
 
    val = readl(&platdata->regs->gpiodir + bank * 2);
    val = val | (1 << pin);
    writel(val, &platdata->regs->gpiodir + bank * 2);
 
    return 0;
}

在使用時采用如下的例子

這里需要注意的是init時的地址！！！一定要與vivado中的進行對應

eg：

xilinx_gpio_init();
xilinx_gpio_direction_output(&axi_gpio_1, 0, 1); //
xilinx_gpio_set_value(&axi_gpio_1, 0, 0);

4)fsbl中使用gpio

這個直接采用sdk中關於gpio的API即可，主要也是位號的選擇及確認