1、在手冊 中 找到 SPI 相關 文檔
2、SPI 相關 說明
46.4.1.1 Functional clock
The LPSPI functional clock is asynchronous to the bus clock and if it remains enabled in
low power modes then LPSPI can perform SPI bus transfers and low power wakeups in
both master and slave modes. The LPSPI divides the functional clock by a prescaler and
the resulting frequency must be at least two times faster than the SPI external clock
(LPSPI_SCK) frequency.
功能時鍾
LPSPI功能時鍾與總線時鍾異步，如果保持啟用狀態，
在低功耗模式下，LPSPI可以在以下情況下執行SPI總線傳輸和低功耗喚醒：
主模式和從模式。 LPSPI將功能時鍾除以預分頻器，然后
產生的頻率必須至少比SPI外部時鍾快兩倍
（LPSPI_SCK）頻率。
46.4.1.2 External clock
The LPSPI shift register is clocked directly by the LPSPI_SCK clock that is either
generated internally in master mode or supplied externally in slave mode.
LPSPI移位寄存器由LPSPI_SCK時鍾直接計時，該時鍾為
在主機模式下內部產生或在從機模式下外部提供。
46.4.1.3 Bus clock
The bus clock is only used for bus accesses to the control and configuration registers. The
bus clock frequency must be sufficient to support the data bandwidth requirements of the
LPSPI registers, including FIFOs.
46.4.1.3總線時鍾
總線時鍾僅用於總線訪問控制和配置寄存器。 的
總線時鍾頻率必須足以支持數據總線的數據帶寬要求
LPSPI寄存器，包括FIFO。
46.4.1.4 Chip reset
The logic and registers for the LPSPI are reset to their default state on a chip reset.
46.4.1.4芯片復位
LPSPI的邏輯和寄存器在芯片復位時復位為默認狀態。
46.4.1.5 Software reset
The LPSPI implements a software reset bit in the Control Register. The CR[RST] will
reset all logic and registers to their default state, except for the CR itself.
46.4.1.5軟件重置
LPSPI在控制寄存器中實現軟件復位位。 CR [RST]將
將所有邏輯和寄存器重置為默認狀態，CR本身除外。
46.4.1.6 FIFO reset
The LPSPI implements write-only control bits that resets the transmit/command FIFO
(CR[RTF] and receive FIFO (CR[RRF]). A FIFO is empty after being reset.
46.4.1.6 FIFO復位
LPSPI實現只寫控制位，該位復位發送/命令FIFO
（CR [RTF]和接收FIFO（CR [RRF]）。FIFO復位后為空。
三：主機模式 功能講解
46.4.2.1 Transmit and Command FIFO
The transmit and command FIFO is a combined FIFO that includes both transmit data
and command words. Command words are stored to the transmit/command FIFO by
writing the transmit command register. Transmit data words are stored to the transmit/
command FIFO by writing the transmit data register.
發送和命令FIFO是組合的FIFO，其中包括發送數據
和命令字。 命令字通過以下方式存儲到發送/命令FIFO中
寫入發送命令寄存器。 發送數據字被存儲到發送/
通過寫入發送數據寄存器來命令FIFO。
When a command word is at the top of the transmit/command FIFO, the following
actions can occur:
• If the LPSPI is between frames, the command word is pulled from the FIFO and
controls all subsequent transfers.
當命令字位於發送/命令FIFO的頂部時，以下內容
可能發生的動作：
• If the LPSPI is busy and either the existing CONT bit is clear or the new CONTC
value is clear, the SPI frame will complete at the end of the existing word, ignoring
the FRAMESZ configuration. The command word is then pulled from the FIFO and
controls all subsequent transfers (or until the next update to the command word).
•如果LPSPI忙，並且現有的CONT位清零或新的CONTC
值清除后，SPI幀將在現有字的末尾完成，而忽略
FRAMESZ配置。 然后將命令字從FIFO中拉出並
控制所有后續傳輸（或直到下一次更新命令字）。
• If the LPSPI is busy and the existing CONT bit is set and the new CONTC value is
set, the command word is pulled from the FIFO during the last LPSPI_SCK pulse of
the existing frame (based on FRAMESZ configuration) and the frame continues
using the new command value for the rest of the frame (or until the next update to the
command word). When CONTC is set, only the lower 24-bits of the command word
are updated.
置位時，在最后一個LPSPI_SCK脈沖期間，命令字從FIFO中拉出。
現有框架（基於FRAMESZ配置），並且框架繼續
在其余幀中使用新的命令值（或直到下一次更新
命令字）。 設置CONTC時，僅命令字的低24位
已更新。
The current state of the existing command word can be read by reading the transmit
command register. It requires at least three LPSPI functional clock cycles for the transmit
command register to update after it is written (assuming an empty FIFO) and the LPSPI
must be enabled (CR[MEN] is set).
可以通過讀取發送來讀取現有命令字的當前狀態
命令寄存器。 發送至少需要三個LPSPI功能時鍾周期
命令寄存器在寫入后（假定為空FIFO）和LPSPI進行更新
必須啟用（設置CR [MEN]）。
Writing the transmit command register does not initiate a SPI bus transfer, unless the
TXMSK bit is set. When TXMSK is set, a new command word will not be loaded until
the end of the existing frame (based on FRAMESZ configuration) and the TXMSK bit
will be cleared at the end of the transfer.
寫入發送命令寄存器不會啟動SPI總線傳輸，除非
TXMSK位置1。 設置TXMSK時，直到加載新命令字
現有幀的末尾（基於FRAMESZ配置）和TXMSK位
將在轉帳結束時清除。
The following table describes the attributes that are controlled by the command word.
下表描述了由命令字控制的屬性。
The LPSPI initiates a SPI bus transfer when data is written to the transmit FIFO, the
HREQ pin is asserted (or disabled) and the LPSPI is enabled. The SPI bus transfer uses
the attributes configured in the transmit command register and timing parameters from
the clock configuration register to perform the transfer. The SPI bus transfer ends once
the FRAMESZ configuration is reached, or at the end of a word when a new transmit
command word is at the top of the transmit/command FIFO. The HREQ input is only
checked the next time the LPSPI goes idle (completes the current transfer and transmit/
command register is empty).
當數據寫入發送FIFO時，LPSPI啟動SPI總線傳輸。
HREQ引腳被置為有效（或禁用）並且LPSPI被使能。 SPI總線傳輸使用
傳輸命令寄存器中配置的屬性和來自
時鍾配置寄存器執行傳輸。 SPI總線傳輸一次結束
達到FRAMESZ配置，或在新傳輸時在單詞末尾
命令字在發送/命令FIFO的頂部。 HREQ輸入僅
下次LPSPI處於空閑狀態時進行了檢查（完成當前傳輸和發送/
命令寄存器為空）。
The transmit/command FIFO also supports a Circular FIFO feature. This allows the
LPSPI master to (periodically) repeat a short data transfer that can fit within the transmit/
command FIFO, without requiring additional FIFO accesses. When the circular FIFO is
enabled, the current state of the FIFO read pointer is saved and the status flags do not
update. Once the transmit/command FIFO is considered empty and the LPSPI is idle, the
FIFO read pointer is restored with the saved version, so the contents of the transmit/
command FIFO are not permanently pulled from the FIFO while circular FIFO mode is
enabled.
發送/命令FIFO還支持循環FIFO功能。 這允許
LPSPI主站（周期性地）重復進行一次短數據傳輸，使其適合發送/
命令FIFO，而無需其他FIFO訪問。 當循環FIFO為
啟用后，將保存FIFO讀取指針的當前狀態，並且不保存狀態標志
更新。 一旦發送/命令FIFO被認為是空的並且LPSPI處於空閑狀態，則
FIFO讀取指針與保存的版本一起恢復，因此發送/接收的內容
在循環FIFO模式下，命令FIFO不會從FIFO中永久拉出
已啟用。
46.4.2.2 Receive FIFO and Data Match
The receive FIFO is used to store receive data during SPI bus transfers. When RXMSK is
set, receive data is discarded instead of storing in the receive FIFO.
46.4.2.2接收FIFO和數據匹配
接收FIFO用於在SPI總線傳輸期間存儲接收數據。 當RXMSK為
設置后，接收數據將被丟棄，而不是存儲在接收FIFO中。
The receive data is written to the receive FIFO at the end of the frame. During a multiple
word or continuous transfer, the receive data is also written to the receive FIFO at the
same time as new transmit data is read from the transmit FIFO. If the transmit FIFO is
empty during a continuous transfer, the receive data is only written to the receive FIFO
after the transmit FIFO is written or the command register is written to end the frame.
Receive data supports a receive data match function that can match received data against
one of two words or against a masked data word. The data match function can also be
configured to compare only the first one or two received data words since the start of the
frame. Receive data that is already discarded due to RXMSK bit cannot cause the data
match to set and will delay the match on first received data word until after all discarded
data is received. The receiver match function can also be configured to discard all receive
data until a data match is detected, using the CFGR0[RDMO] control bit. When clearing
the CFGR0[RDMO] control bit following a data match, clear CFGR0[RDMO] before
clearing SR[DMF] to allow all subsequent data to be received.
接收數據在幀的末尾寫入接收FIFO。在多次
字或連續傳輸時，接收數據也將在以下位置寫入接收FIFO：
與從發送FIFO中讀取新的發送數據的時間相同。如果發送FIFO為
在連續傳輸期間為空，接收數據僅寫入接收FIFO
在寫入發送FIFO或寫入命令寄存器以結束幀之后。
接收數據支持接收數據匹配功能，可以將接收到的數據與
兩個字之一或針對屏蔽數據字。數據匹配功能也可以是
配置為僅比較自開始以來的第一個或兩個接收到的數據字
幀。接收由於RXMSK位已被丟棄的數據不會導致數據
設置匹配項，將延遲對第一個接收到的數據字的匹配，直到全部丟棄
數據已接收。接收器匹配功能也可以配置為丟棄所有接收
使用CFGR0 [RDMO]控制位，直到檢測到數據匹配為止。清理時
數據匹配之后的CFGR0 [RDMO]控制位，在清除CFGR0 [RDMO]之前
清除SR [DMF]以允許接收所有后續數據。
46.4.2.3 Timing Parameters
The following table lists the timing parameters that are used for all SPI bus transfers,
these timing parameters are relative to the LPSPI functional clock divided by the
PRESCALE configuration. Although the Clock Configuration Register cannot be
changed when the LPSPI is busy, the PRESCALE configuration can be altered between
transfers using the command register, to support interfacing to different slave devices at
different frequencies.
46.4.2.3時序參數
下表列出了用於所有SPI總線傳輸的時序參數，
這些時序參數相對於LPSPI功能時鍾除以
PRESCALE配置。 雖然時鍾配置寄存器不能
如果在LPSPI繁忙時更改了PRESCALE配置，則可以在
使用命令寄存器進行傳輸，以支持與不同從設備的接口
不同的頻率。
46.4.2.4 Pin Configuration
The LPSPI_SIN and LPSPI_SOUT pins can be configured via the PINCFG configuration
to swap directions or even support half-duplex transfers on the same pin.
The OUTCFG configuration can be used to determine if output data pin (eg:
LPSPI_SOUT) will tristate when the LPSPI_PCS is negated, or if it will simply retain the
last value. When configuring for half-duplex transfers using the same data pin in single
bit transfer mode, or any transfer in 2-bit and 4-bit transfer modes, then the output data
pins must be configured to tristate when LPSPI_PCS is negated.
The PCSCFG configuration is used to disable LPSPI_PCS[3:2] functions and to use them
for quad-data transfers. This option must be enabled when performing quad-data
transfers.
可以通過PINCFG配置來配置LPSPI_SIN和LPSPI_SOUT引腳
交換方向，甚至在同一引腳上支持半雙工傳輸。
OUTCFG配置可用於確定輸出數據引腳（例如：
當LPSPI_PCS取反時，或者如果僅保留LPSPI_PCS，LPSPI_SOUT）將進入三態。
最后的值。 在單個配置中使用相同的數據引腳配置半雙工傳輸時
位傳輸模式，或2位和4位傳輸模式下的任何傳輸，然后輸出數據
LPSPI_PCS取反時，必須將引腳配置為三態。
PCSCFG配置用於禁用LPSPI_PCS [3：2]功能並使用它們
用於四元數據傳輸。 執行四元數據時必須啟用此選項
轉移。
46.4.2.5 Clock Loopback
The LPSPI master can be configured to use one of two clocks to sample the input data
(eg: LPSPI_SIN), either the LPSPI_SCK output clock directly or a delayed version of
this clock. The delayed version of the LPSPI_SCK is delayed by the LPSPI_SCK pin
output delay, plus the LPSPI_SCK pin input delay, and is configured by setting
CFGR1[SAMPLE]. Enabling the loopback version of the LPSPI_SCK can improve the
setup time of the input data from the slave.
46.4.2.5時鍾環回
可以將LPSPI主器件配置為使用兩個時鍾之一來采樣輸入數據
（例如：LPSPI_SIN），可以直接使用LPSPI_SCK輸出時鍾，也可以使用延遲版本
這個時鍾。 LPSPI_SCK的延遲版本由LPSPI_SCK引腳延遲
輸出延遲加上LPSPI_SCK引腳輸入延遲，通過設置
CFGR1 [SAMPLE]。 啟用LPSPI_SCK的環回版本可以改善
從站輸入數據的建立時間。
四：SPI 時鍾源 選擇
四種 時鍾源 來源
