時鍾信號的占空比調整——Verilog

時鍾信號的占空比調整——Verilog

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: chensimin
// 
// Create Date: 2018/10/16 11:09:15
// Design Name: 
// Module Name: duty_regulate
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module duty_regulate(

    input     wire     clk,
    input     wire     rst,

    output    wire     SCL_POS,
    output    wire     SCL_HIG,
    output    wire     SCL_NEG,
    output    wire     SCL_LOW
    );

//-------------------------------------------------
//首先規定一個時鍾周期的長度 512
reg [10:0]start_cnt = 0;

always @(posedge clk or posedge rst)
begin
    if(rst)
        start_cnt <= 11'd0;
    else if(start_cnt == 11'd511)
        start_cnt <= 11'd0;
    else 
        start_cnt <= start_cnt + 1'b1;
end

//-------------------------------------------------
//當計數器計數到0時，SCL_HIG即整個高電平的中點
//當計數器計數到127時，SCL_NEG即時鍾的下降沿
//當計數器計數到255時，SCL_LOW即時鍾整個低電平的中點
//當計數器計數到382時，SCL_POS即時鍾的上升沿
//結論：通過調整時鍾上升沿，下降沿，高電平中點，低電平中點的位置，即可以調整整個時鍾的占空比
reg [2:0]cnt = 3'd5;
always @(posedge clk or posedge rst)
begin
    if(rst)
        cnt <= 3'd5;
    else 
    begin
        case(start_cnt)
            11'd0 :  cnt <= 3'd1;
            11'd127:  cnt <= 3'd2;
            11'd255:  cnt <= 3'd3;
            11'd382:  cnt <= 3'd0;
            default:  cnt <= 3'd5;
        endcase
    end 
end

//-------------------------------------------------

assign  SCL_POS    =    (cnt==3'd0);        
assign  SCL_HIG    =    (cnt==3'd1);        
assign  SCL_NEG    =    (cnt==3'd2);        
assign  SCL_LOW =    (cnt==3'd3);

endmodule




/*

add_force {/duty_regulate/clk} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps
add_force {/duty_regulate/rst} -radix hex {1 0ns} {0 200ns}


*/

仿真結果：