Link帶參數的Verilog模塊（Design Compiler）

在Design Compiler中，Verilog文件可以用read_verilog命令讀入，用link命令連接。以下是連接兩個文件RegisterFile.v和Test.v的腳本：

# Read design files
file mkdir ./work
define_design_lib WORK -path ./work
read_verilog {RegisterFile.v Test.v}
current_design Test
link

其中define_design_lib指定中間文件存放到work目錄，否則默認會存放到當前目錄，文件多了看起來比較混亂。另外，建議使用current_design命令顯式指定當前模塊。

如果沒有使用參數(Parameter)，這個腳本工作的很好，但是一旦在例化模塊時指定了參數值，則會出錯：

Information: Building the design 'RegisterFile' instantiated from design 'Test' with
	the parameters "2,1". (HDL-193)
Warning: Cannot find the design 'RegisterFile' in the library 'WORK'. (LBR-1)
Warning: Unable to resolve reference 'RegisterFile' in 'Test'. (LINK-5)
0

 查看前面的信息也會發現，實際上模塊是使用默認參數例化的，所以連接時找不到被例化模塊的實現：

Inferred memory devices in process
	in routine RegisterFile line 21 in file
		'./rtl/RegisterFile.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    RegArray_reg     | Flip-flop | 1024  |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine RegisterFile line 33 in file
		'./rtl/RegisterFile.v'.
=================================================================================
|     Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
=================================================================================
| LatchedReadAddr_1_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| LatchedReadAddr_2_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
=================================================================================

那么，使用了帶參數的模塊，就要使用analyze和elaborate命令連接，腳本如下：

# Read design files
file mkdir ./work
define_design_lib WORK -path ./work
analyze -format verilog {RegisterFile.v Test.v}
elaborate Test

現在查看輸出信息，就會發現確實是按照例化時指定的參數編譯模塊的，並且連接成功了：

Inferred memory devices in process
	in routine RegisterFile_W_DATA2_W_ADDR1 line 21 in file
		'./rtl/RegisterFile.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    RegArray_reg     | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine RegisterFile_W_DATA2_W_ADDR1 line 33 in file
		'./rtl/RegisterFile.v'.
=================================================================================
|     Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
=================================================================================
| LatchedReadAddr_1_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
| LatchedReadAddr_2_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
=================================================================================
Presto compilation completed successfully.
1

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