(轉)RISC-V結構邏輯圖


轉載地址:http://blog.csdn.net/zzwu/article/details/54810162

 

 

說明:

執行6級流水作業:

1. fetch(取指)

2. decode(譯碼)

3. dispatch/renaming(分發/重命名)

4. select/wakeup(選擇/喚醒)

5. execution/mem access/finish(執行/存取/結束)

6. complete/retire(完成/恢復)

 

六級流水作業的另一種划分說法:

The six-stage pipeline should be divided into the following stages:

  • Instruction Fetch (取指)-- request instruction from iMem and update PC
  • Decode(譯碼) -- receive response from iMem and decode instruction
  • Register Fetch(取寄存器) -- read from the register file
  • Execute(執行) -- execute the instruction and redirect the processor if necessary
  • Memory(存儲) -- send memory request to dMem
  • Write Back(回寫) -- receive memory response from dMem (if applicable) and write to register file


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