(转)RISC-V结构逻辑图


转载地址:http://blog.csdn.net/zzwu/article/details/54810162

 

 

说明:

执行6级流水作业:

1. fetch(取指)

2. decode(译码)

3. dispatch/renaming(分发/重命名)

4. select/wakeup(选择/唤醒)

5. execution/mem access/finish(执行/存取/结束)

6. complete/retire(完成/恢复)

 

六级流水作业的另一种划分说法:

The six-stage pipeline should be divided into the following stages:

  • Instruction Fetch (取指)-- request instruction from iMem and update PC
  • Decode(译码) -- receive response from iMem and decode instruction
  • Register Fetch(取寄存器) -- read from the register file
  • Execute(执行) -- execute the instruction and redirect the processor if necessary
  • Memory(存储) -- send memory request to dMem
  • Write Back(回写) -- receive memory response from dMem (if applicable) and write to register file


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