VHDL調用Verilog模塊的時候，要在實例化模塊前，加上“verilogmodelGM： ”
VHDL調用verlog
verilog module：
module m(a,b,c);
input a,b;
output c;
...
endmodule
調用如下：
compoent m
port( a: in std_logic;
b: in std_logic;
c: out std_logic
);
end compoent
begin
verilogmodelGE: m
port map
(...
)
...
end
在VHDL里調用Verilog的話：例化+映射
在Verilog里調用VHDL的話：只要映射
看的別人的。。。所以是錯誤的
正確方法：
這里用VHDL調用VERILOG寫好的模塊.
先按VHDL的語法聲明實體（也就是你用Verilog寫的模塊），然后按VHDL的語法例化實體就行了 .
這樣就不用轉換了,或者可以少用轉換了.
例子.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.dt16_pkg.all;
entity clk_alm is
port (
reset : in std_logic;
fck32m : in std_logic; --來自背板的32M幀頭
clk32m : in std_logic; --來自背板的32M時鍾
refclk2m : in std_logic; --2M參考時鍾
clklos : out std_logic --時鍾告警輸出
);
end clk_alm;
architecture arch_clk_alm of clk_alm is
component clk_dog
port(
reset : in std_logic;
clock : in std_logic;--work clock
refclk : in std_logic;--reference clock
alm : out std_logic
);
end component;
component ALM --聲明
port( XMCLK : in std_logic;
RST : in std_logic;
M_CLK : in std_logic;
LOST_ALM : out std_logic
);
end component;
signal alm_clk: std_logic;
signal alm_fck: std_logic;
signal refclk2m_div: std_logic;
signal count: std_logic_vector(2 downto 0);
signal delay_los: std_logic;
begin
clk_dog0: clk_dog
port map (
reset => reset ,
clock=>clk32m ,
refclk =>refclk2m ,
alm =>alm_clk
);
fck_dog0: ALM --例化
PORT MAP(
XMCLK => fck32m ,
RST => reset ,
M_CLK => refclk2m_div ,
LOST_ALM => alm_fck
);
process(reset,refclk2m)
begin
if reset='1' then
count<=(others=>'0');
elsif refclk2m'event and refclk2m='1' then
count<=count+1;
end if;
end process;
refclk2m_div<=count(2);
clklos<=not(alm_clk and alm_fck);
end arch_clk_alm;
-----------------以下是verilog寫的module-----------------
module ALM (XMCLK, RST, M_CLK, LOST_ALM);
input XMCLK ;
input RST ;
input M_CLK ;
output LOST_ALM ;
reg LOST_ALM;
reg [2:0]ALM_STATE;
reg [2:0]COUNTA;
reg [2:0]COUNTB;
reg [2:0]COUNTC;
always @(negedge RST or posedge XMCLK)
begin
if (!RST)
COUNTA <= 0;
else if (COUNTA == 7)
COUNTA <= 0;
else COUNTA <= COUNTA + 1;
end
always @(posedge M_CLK)
begin
if (!RST)
begin
COUNTB <= 0;
COUNTC <= 0;
end
else
begin
COUNTC <= COUNTB;
COUNTB <= COUNTA;
end
end
always @(negedge M_CLK)
begin
if (!RST)
ALM_STATE <= 0;
else if (ALM_STATE == 7)
ALM_STATE <= 0;
else if (COUNTC == COUNTB)
ALM_STATE <= ALM_STATE + 1;
else ALM_STATE <= 0;
end
always @(posedge M_CLK)
begin
if (!RST)
LOST_ALM <= 1;
else if (ALM_STATE == 7)
LOST_ALM <= 0;
else LOST_ALM <= 1;
end
endmodule
其實不僅verilog 可以與 vhdl 混合使用，而且與原理圖也能混合使用，就是傳說中的分層設計，底層模塊隨便你用什么，生成符號就成，然后到頂層調用，頂層可用原理圖也可用語言，目前altera的quartus、xilinx的ise、lattice的isplever均支持這種模式。