In typical modern DRAM systems, thememory controller periodically issues anauto-refresh (auto-refreshis sometimes called CAS-before-RAS refresh)command to the DRAM.The DRAM chip thenchooses which rows to refresh using an internal counter, and refreshes a numberof rows based on the device capacity. During normal temperature operation (below 85’C), the average time between auto-refresh commands(called tREFI ) is 7.8us . In the extended temperature range (between 85 _C and 95 _C), the temperature range in whichdense server environments operate [10] and 3D-stacked DRAMs are expected tooperate [1], the time between
auto-refresh commands is halved to 3.9 us [15]. An auto-refresh operation occupies all banks on the ranksimultaneously (preventing the rank from servicing any requests) for a lengthof time tRFC, where tRFC depends on the number of rows beingrefreshed.
Previous DRAM generationsalso allowed the memory controller to perform refreshes byopening rows one-by-one (calledRAS-only refresh [30]), butthismethod has been deprecated due to the additional powerrequired to send row addresses on the bus.
Some devices support per-bank refreshcommands, which refresh several rows at a single bank [16], allowing forbank-level parallelism at a rank during refreshes. However, this feature is notavailable in most DRAM devices.
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JEDEC standards [1] specify that DRAM devices must be refreshed every 64 millisecond (32 millisecond at above 85‘C temperature). All the DRAM rows must undergo refresh within this time period. The total time incurred in doing refresh is thus proportional to the number of rows in memory, and approximately doubles as the number of rows in the DRAM array is doubled. Initial DRAM designs performed Burst Refreshes whereby refresh for all DRAM rows happened in succession; however, this mode makes memory unavailable for a long periods of time. To avoid this long latency,JEDEC standards support Distributed Refresh mode. In this mode, the total number of rows in a bank is divided into 8K groups, and each group is refreshed within a time period equal to 7.8 μsecond (3.9 μsecond at high temperatures). This time duration is referred to as Refresh Interval or TREFI . The DRAM controller sends a refresh pulse to DRAM devices once every TREFI . The standard for TREFI was developed when memory banks typically had 8K rows; therefore each refresh pulse refreshed exactly one row. Over time, as the size of memory has increased, the TREFI has remained the same, only the number of rows refreshed per refresh pulse has increased.
For example, for the 8Gb DRAM chips we consider, each refresh pulse refreshes 8-16 rows. Therefore, the latency
to do refresh for one group is almost an order of magnitude longer than a typical read operation.
在典型的現代dram系統中，MC周期性的向dram發送auto-refresh(有時候這這種刷新方式稱為CAS-before-RAS刷新)命令。Dram芯片使用一個內部計數器，來選擇需要刷新哪些行，每一次刷新的行數和Dram的容量有關。在正常溫度下(低於85‘C)，auto-refresh命令的時間間隔(稱為tREFI)為7.8us，在高溫下(介於85’C和95‘C，通常密集的服務器環境和3D dram處於這種溫度下)，時間間隔為3.9us.一個auto-refresh操作同時占有一個rank的所有的bank(使rank不能相應任何內存請求)的時間為tRFC(注意：tRFC為刷新所占用的時間，而tREFI為兩次刷新的時間間隔)，而tRFC取決於刷新的行數。（注：這種方式最為常見）
以前的Dram也允許MC通過一行一行的打開每一行的方式執行刷新操作(稱為RAS-only刷新)，但是由於需要額外的功耗來向總線傳送行地址，所以這種方式被廢棄了。
有的Dram也支持每個bank刷新的命令，每次同時刷新一個bank的多個行，在一個rank刷新的時候允許bank-level 並行(注：這指的是刷新rank中的一個bank的時候，可以訪問這個rank的另外一個bank)。
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JEDEC(聯合電子設備工程會議 Joint Electron Device Engineering Council ) 規定必須在64ms內對每一行至少刷新一次，刷新所占的時間與內存中的行數成比例，如果dram中的行數加倍的話，那么刷新所占的時間也大約提高一倍，有集中式刷新(Burst Refresh)和分布式刷新(Distributed Refresh)。為了避免過長的"死時間"，JEDEC也支持分布式刷新，在這種刷新模式下，一個bank中的所有row被分成一些具有8K個row的組，每個組在7.8us(高溫情況下，沒隔3.9us刷新一次)會被刷新一次。7.8us(或者3.9us
這個tREFI)是在每個bank有8K個行（即 64ms = 7.8us × 8 × 1024）時提出來的，這是基本上就是每個刷新脈沖刷新一個行。但是，隨着dram容量的增加，tREFI保持不變，但是每個刷新脈沖需要刷新的行數增加。比如說，對於8Gb的dram，每個刷新脈沖需要刷新8-16個行。因此，每個tREFI時間內，花在刷新的時間大概是一次讀操作所花時間的10倍左右（這是因為，刷新一行的時間和一次讀操作的時間相同）。
參考資料：
RAIDR: Retention-Aware Intelligent DRAM Refresh,Jamie Liu Ben Jaiyen Richard Veras Onur Mutlu
Carnegie Mellon University
{jamiel,bjaiyen,rveras,onur}@cmu.edu
A Case for Refresh Pausing in DRAM Memory Systems
Prashant Nair Chia-Chen Chou Moinuddin K. Qureshi
School of Electrical and Computer Engineering Georgia Institute of Technology
{pnair6, cchou34, moin}@gatech.edu