vhdl rising_edge(clk) (clk'event and clk='1')的區別

http://vhdlguru.blogspot.com/2010/04/difference-between-risingedgeclk-and.html

 

rising_edge 是非常嚴格的上升沿，必須從0到1 ，    (clk'event and clk='1')可以從X到1

查看rising_edge原型

 

    FUNCTION rising_edge  (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
    BEGIN
        RETURN (s'EVENT AND (To_X01(s) = '1') AND
                            (To_X01(s'LAST_VALUE) = '0'));
    END;

the statement (clk'event and clk='1') results TRUE when the present value is '1' and there is an edge transition in the clk.It doesnt see whether the previous value is '0' or not.