JTAG - Joint Test Action Group
JTAG(Joint Test Action Group)聯合測試行動小組)是一種國際標准測試協議（IEEE 1149.1兼容）
Test Access Port and Boundary-Scan Architecture
主要用於芯片內部測試及對系統進行仿真、調試。現在多數的高級器件都支持JTAG協議，如DSP、FPGA器件等。通常所說的JTAG大致分兩類，
一類用於測試芯片的電氣特性，檢測芯片是否有問題；
一類用於Debug；一般支持JTAG的CPU內都包含了這兩個模塊。
一個含有JTAG Debug接口模塊的CPU，只要時鍾正常，就可以通過JTAG接口訪問CPU的內部寄存器和掛在CPU總線上的設備
標准的JTAG接口是4線：TMS、 TCK、TDI、TDO，分別為模式選擇、時鍾、數據輸入和數據輸出線。
ARM系統的JTAG接口
接口是一個20腳的IDC插座。下表給出了具體的信號說明
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序號
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信號名
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方向
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說 明
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1
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Vref
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Input
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接口電平參考電壓，通常可直接接電源
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2
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Vsupply
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Input
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電源
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3
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nTRST
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Output
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(可選項) JTAG復位。在目標端應加適當的上拉電阻以防止誤觸發。
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4
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GND
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--
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接地
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5
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TDI
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Output
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Test Data In from Dragon-ICE to target.
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6
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GND
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--
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接地
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7
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TMS
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Output
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Test Mode Select
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8
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GND
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--
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接地
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9
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TCK
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Output
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Test Clock output from Dragon-ICE to the target
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10
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GND
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--
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接地
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11
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RTCK
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Input
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(可選項) Return Test Clock。由目標端反饋給Dragon-ICE的時鍾信號，用來同步TCK信號的產生。不使用時可以直接接地。
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12
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GND
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--
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接地
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13
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TDO
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Input
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Test Data Out from target to Dragon-ICE.
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14
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GND
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--
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接地
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15
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nSRST
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Input/Output
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(可選項) System Reset，與目標板上的系統復位信號相連。可以直接對目標系統復位，同時可以檢測目標系統的復位情況。為了防止誤觸發，應在目標端加上適當的上拉電阻。
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16
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GND
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--
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接地
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17
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NC
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保留
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|
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18
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GND
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--
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接地
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19
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NC
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--
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保留
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20
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GND
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--
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接地
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ITM - instrumentation trace macrocell
General description
The ITM is an application-driven trace source that supports printf style debugging
to trace Operating System (OS) and application events, and emits diagnostic system information.
The ITM emits trace information as packets which can be generated as:
● Software trace. Software can write directly to the ITM stimulus registers to emit packets.
● Hardware trace. The DWT generates these packets, and the ITM emits them.
● Time stamping. Timestamps are emitted relative to packets.
The ITM contains a 21-bit counter to generate the timestamp.
The Cortex™-M3 clock or the bit clock rate of the Serial Wire Viewer (SWV) output clocks the counter.
The packets emitted by the ITM are output to the TPIU (Trace Port Interface Unit).
The formatter of the TPIU adds some extra packets (refer to TPIU) and
then output the complete packets sequence to the debugger host.
The bit TRCEN of the Debug Exception and Monitor Control Register must be enabled before you program or use the ITM.
ETM - embedded trace macrocell
General description
The ETM enables the reconstruction of program execution.
Data are traced using the Data Watchpoint and Trace (DWT) component or
the Instruction Trace Macrocell (ITM) whereas instructions are traced
using the Embedded Trace Macrocell (ETM).
The ETM transmits information as packets and is triggered by embedded resources.
These resources must be programmed independently and the trigger source
is selected using the Trigger Event Register (0xE0041008).
An event could be a simple event (address match from an address comparator)
or a logic equation between 2 events.
The trigger source is one of the fourth comparators of the DWT module,
The following events can be monitored:
● Clock cycle matching
● Data address matching
For more informations on the trigger resources refer to Section 31.13: DWT (data watchpoint trigger).
The packets transmitted by the ETM are output to the TPIU (Trace Port Interface Unit).
The formatter of the TPIU adds some extra packets
and then outputs the complete packet sequence to the debugger host.
DWT - data watchpoint and trace
The DWT unit consists of four comparators. They are configurable as:
● a hardware watchpoint or
● a trigger to an ETM or
● a PC sampler or
● a data address sampler
The DWT also provides some means to give some profiling informations.
For this, some counters are accessible to give the number of:
● Clock cycle
● Folded instructions
● Load store unit (LSU) operations
● Sleep cycles
● CPI (clock per instructions)
● Interrupt overhead
TPIU (trace port interface unit)
The TPIU acts as a bridge between the on-chip trace data from the ITM and the ETM.
The output data stream encapsulates the trace source ID,
that is then captured by a trace port analyzer (TPA).
The core embeds a simple TPIU, especially designed for low-cost debug
(consisting of a special version of the CoreSight TPIU).
Serial Wire Debug (SWD)
SWD為pin有限的應用提供了一個調試的端口，主要是面向small package的微控制器，
也面向復雜的ASICs—pin數量有限並且成本控制的應用。
SWD使用一個時鍾+雙向數據管腳來取代5-pin的JTAG端口，提供了所有的通用的JTAG調試和測試功能，
並且增加了：在沒有中斷內核以及沒有增加額外的代碼的情況下，對系統內存的實時訪問。
SWD使用了一個ARM標准的雙向有線協議，這已在ARM Debug Interface v5中定義。
SWD在調試器和目標系統之間用一種高效標准的方式互相傳送數據。它是ARM-based設備的標准接口。
SWD提供了一種簡單可靠的從JTAG的移植，只需在TMS和TCK管腳上覆蓋SWDIO和SWCLK信號，
允許雙模的設備，這可以提供另外的JTAG信號。在SWD模式中，這些額外的JTAG管腳可被用來作其他的用途。
SWD和所有的ARM核以及所有的使用JTAG的核兼容，並且在Cortex核以及CoreSight調試架構中提供了對調試寄存器的訪問。
Serial Wire Output(SWO)
支持Serial Wire Output(SWO)意思是指支持從core引出一個pin的輸出信號。
這個功能目前只在Cortex-M3上測試通過。 它這意味着更快的傳輸速度，並且不會中斷程序的執行。
Serial Wire Viewer(SWV)
Serial Wire Output(SWO) 和 Instrumentation Trace Macrocell(ITM) 可以用來共同構成一個Serial Wire Viewer(SWV)。
SWV提供了一種低成本的從MCU獲得信息的方法。
SWO可用兩種格式輸出調試信息，但在一個時間只能輸出一種格式的調試信息。
這兩種編碼方式是UART和曼徹斯特編碼。
SWV使用SWO pin來傳輸不同的信息包。在Cortex-M3 Core中，有三種源信息可以通過此pin來傳輸：
對應用驅動跟蹤源（支持printf格式的調試）的ITM，它支持32路通道，使得其可以用於例如real-time kernal信息的其他用途。
對實時變量的監測以及PC-sampling的Data Watchpoint和Trace(DWT)，這可以用來定時的輸出PC或者CPU內部不同計數器的值，
可以用來從目標板獲得分析信息。
Timestamping。和包有關的Timestamping。
The Serial Wire Debug mode is an alternative to the standard JTAG interface.
SWD uses 2-pins to provide the same debug functionality as JTAG with no performance penalty,
and introduces data trace capabilities with the Serial Wire Viewer (SWV).
The SWD interface pins can be overlayed with the JTAG signals, allowing the standard target connectors to be used.
- TCLK - SWCLK (Serial Wire Clock)
- TMS - SWDIO (Serial Wire debug Data Input/Output)
- TDO - SWO (output pin for Serial Wire Viewer)
STM32 - SWJ debug port ( SWD and JTAG)
The STM32 core integrates the Serial Wire / JTAG Debug Port (SWJ-DP).
It is an ARM standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and
a SWDP (2-pin) interface.
The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHPAP port.
The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the AHP-AP port.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO.
This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP.
SWD and JTAG selection mechanism
SWJ-DP enables one of the following modes to be selected:
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JTAG protocol
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Serial Wire Debug protocol
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Dormant.
When in Dormant mode, the TMS, TDI, and TDO signals can be used for other purposes,
enabling alternative debug protocols to be used by other devices connected to the same pins.
The switcher defaults to JTAG operation on power-on reset, therefore
the JTAG protocol can be used from reset without sending a selection sequence.
The SWJ-DP contains a mode status output, JTAGNSW,
that is HIGH when the SWJ-DP is in JTAG mode and LOW when in SWD or Dormant mode.
This signal can be used to:
-
disable other TAP controllers when the SWJ-DP is in SWD or Dormant mode,
for example by disabling TCK or forcing TMS HIGH -
multiplex the Serial Wire output, TRACESWO,
onto another pin such as TDO when not in JTAG mode.
Another status output, JTAGTOP, indicates the state of the JTAG-DP TAP controller. These states are:
-
Test-Logic-Reset
-
Run-Test/Idle
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Select-DR-Scan
-
Select-IR-Scan.
This signal can be used with JTAGNSW to control multiplexers so that,
for example, TDO and TDI can be reused as General Purpose Input/Output (GPIO) signals
when the device is not in JTAG mode, or during cycles when these signals are not in use by the JTAG-DP TAP controller.
By default, the JTAG-Debug Port is active.
If the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG sequence on TMS/TCK
(respectively mapped to SWDIO and SWCLK) which disables the JTAG-DP and enables the SW-DP.
This way it is possible to activate the SWDP using only the SWCLK and SWDIO pins.
This sequence is:
1. Send more than 50 TCK cycles with TMS (SWDIO) =1
2. Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted first)
3. Send more than 50 TCK cycles with TMS (SWDIO) =1
STM32 - JTAG TAP connections
