Quartus報錯之Error (10822): HDL error at mintue.vhd(37): couldn't implement registers for assignments on this clock edge

今天用vhdl寫數字時鍾顯示器：出現以下問題：

1、Error (10822): HDL error at mintue.vhd(37): couldn't implement registers for assignments on this clock edge

 

一個進程只能有一個上升沿判別語句；

process中如果有兩個以上的判別語句，則出現以上錯誤；

 

 

Error (10821): HDL error at mintue.vhd(19): can't infer register for "count_6[2]" because its behavior does not match any supported register model