今天用vhdl写数字时钟显示器：出现以下问题：
1、Error (10822): HDL error at mintue.vhd(37): couldn't implement registers for assignments on this clock edge
一个进程只能有一个上升沿判别语句；
process中如果有两个以上的判别语句，则出现以上错误；
Error (10821): HDL error at mintue.vhd(19): can't infer register for "count_6[2]" because its behavior does not match any supported register model