错误原因：端口声明错误
解决办法：比如input端口不能被定义为reg类型
Error (10278): Verilog HDL Port Declaration error at **.v(21): input port "**" cannot be declared with type ""
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模块端口输出不能到REG寄存器，[Synth 8-685] variable 'reg_clkd1m2_rx_lvds_clock' should not be used in output port connection ["E:/PJ/2021_8_13/top_2k4k_v1/gsv_7a15/gsv_7a15.srcs/sources_1/new/rx_lvds_8bit.v":232]
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