vivado implementation執行時候報錯：Unsupported PLLE2_ADV connectivity.......

執行時候出錯，

[DRC REQP-1712] Input clock driver: Unsupported PLLE2_ADV connectivity. The signal u_clk_wiz_0/inst/clk_in1 on the u_clk_wiz_0/inst/plle2_adv_inst/CLKIN1 pin of u_clk_wiz_0/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.

 

 

由提示信息可知，應該是配置clocking wizard出問題了。

 

解決辦法：

選擇PLL后，將source由“single ended clock capable pin”調為“global buffer”即可。再次implementation時候就不報錯了。