1、[Synth 8-2543] port connections cannot be mixed ordered and named
說明例化時最后一個信號添加了一個逗號。
2、
原因：報告說明有一個管腳沒有進行分配。
3、
從文件列表中發現
當一些文件的路徑改變后，原來文件路徑因為找不到文件的就會報紅，新的文件不會自動替換原來的文件，這一點一定要注意，一定要手動刪除。
4、
把約束文件.xdc內關於DEGUG core的信息全部刪除后保存，再運行軟件，彈出的界面話詢問是save,還是load.
5、
在運行程序的時候點擊，就會停止運行，所以一般不要點。
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u5_adc_module/adc1_in_clk_in] >
u5_adc_module/u1_IBUFGDS_inst (IBUFDS.O) is locked to IOB_X1Y146 and u5_adc_module/u1_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
該問題的解決辦法：set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u5_adc_module/adc1_in_clk_in]
[Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 5 out of 89 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led_alm, led_iso, led_agc, dn_pa_sw, up_pa_sw. 幾個信號沒有分配引腳
[IP_Flow 19-3805] Failed to generate and synthesize debug IP "xilinx.com:ip:xsdbm:1.0".
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [Common 17-680] Path length exceeds 260-Byte maximum allowed by Windows: f:/Company_Prj/Date201509/xilinx_ics_100t/xilinx_wireless_ics_prj0915/xilinx_wireless_35t_prj0915/xilinx_wireless_35t_prj0915.runs/impl_1/.Xil/Vivado-12912-RD-PC/dbg_hub_CV.0/run/.srcs/sources_1/ip/dbg_hub_CV/fifo_generator_v12_0/hdl/fifo_generator_v12_0_vhsyn_rfs.vhd
[Chipscope 16-119] Implementing debug core dbg_hub failed.
ERROR: Could not generate core for dbg_hub. Aborting IP Generation operation.
ERROR: [Chipscope 16-218] An error occurred while trying to create or get a cached instance from the IP cache manager:
"IP generation failed see log file in f:/Company_Prj/Date201509/xilinx_ics_100t/xilinx_wireless_ics_prj0915/xilinx_wireless_35t_prj0915/xilinx_wireless_35t_prj0915.runs/impl_1/.Xil/Vivado-12912-RD-PC/dbg_hub_CV.0/out
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [Common 17-680] Path length exceeds 260-Byte maximum allowed by Windows: f:/Company_Prj/Date201509/xilinx_ics_100t/xilinx_wireless_ics_prj0915/xilinx_wireless_35t_prj0915/xilinx_wireless_35t_prj0915.runs/impl_1/.Xil/Vivado-12912-RD-PC/dbg_hub_CV.0/run/.srcs/sources_1/ip/dbg_hub_CV/fifo_generator_v12_0/hdl/fifo_generator_v12_0_vhsyn_rfs.vhd
"
解決問題的辦法：由於文件路徑太長。把文件路徑改短
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# ** Error: ./../../../H27V0-1SC-V02.srcs/sources_1/ip/coe_fifo/fifo_generator_v12_0/hdl/fifo_generator_v12_0.vhd(46)): in protected region.
# ** Error: ./../../../H27V0-1SC-V02.srcs/sources_1/ip/coe_fifo/fifo_generator_v12_0/hdl/fifo_generator_v12_0.vhd(46)): in protected region.
# ** Error: ./../../../H27V0-1SC-V02.srcs/sources_1/ip/coe_fifo/fifo_generator_v12_0/hdl/fifo_generator_v12_0.vhd(46)): in protected region.
對於這樣的問題目前只能重建工程了
這種情況說明抓數據的文件和當前開發板中的文件是不對應的，應該重新燒寫程序