一、參考模型
- 圖源來自《【搶先版】小梅哥FPGA時序約束從遙望到領悟》
二、參數分析
- T(0)->(3) = Tclk1
- T(3)->(4) = Tco
- T(4)->(5) + T(5)->(6) = Tdata
- T(4)->(5) = Tdata(Init)
- T(5)->(6) = Tdata(Pcb)
- T(5)->(6)
- T(0)->(1) + T(1)->(7) = Tclk2
- T(0)->(1) = Tclk2(Init)
- T(1)->(7) = Tclk2(Pcb)
(4)->(5)的走線是在FPGA芯片內部（IC）
(5)->(6)的走線是在PCB板上
(0)->(1)的走線是在FPGA芯片內部（IC）
(1)->(7)的走線是在PCB板上
計算PCB板上電信號的傳輸時間，可以將電信號等效為光速，得到的電信號傳輸時間與長度關系的參數為5555mil/ns
1mil = 0.0254mm
5555mil/na -> 141.097mm/ns
三、建立時間余量分析 Slack(Tsu)
- Data Require Time(數據要求時間) = Tclk2 - Tsu(芯片數據建立時間) + Latch edge(接收沿) = Tclk2(Init) + Tclk2(Pcb) - Tsu + Latch edge(接收沿)
- Data Arrival Time(數據到達時間) = Tclk1 + Tco + Tdata + Launch edge(發送沿) = Tclk1 + Tco + Tdata(Init) + Tdata(Pcb) + Launch edge(發送沿)
- Latch edge(接收沿) - Launch edge(發送沿) = Tclk（因為是一個時鍾，所以相減就是時鍾周期）
- Slack(Tsu)
- Data Require Time - Data Arrival Time = (Tclk2 - Tsu + Latch edge) - (Tclk1 + Tco + Tdata + Launch edge)
- Data Require Time - Data Arrival Time = (Tclk2(Init) + Tclk2(Pcb) - Tsu + Latch edge) - (Tclk1 + Tco + Tdata(Init) + Tdata(Pcb) + Launch edge)
- Data Require Time - Data Arrival Time = (Tclk2(Init) + Tclk2(Pcb) - Tsu) - (Tclk1 + Tco + Tdata(Init) + Tdata(Pcb)) + Tclk
- Data Require Time - Data Arrival Time >= 0
- Tclk2(Init) - Tclk1 -Tco - Tdata(Init) >= -Tclk2(Pcb) + Tsu +Tdata(Pcb) - Tclk （注：左邊是未知量，右邊是可知量）
- Tclk2(Init) - Tclk1 -Tco - Tdata(Init) + Tclk >= -Tclk2(Pcb) + Tsu +Tdata(Pcb)
- -Tclk2(Pcb) + Tsu +Tdata(Pcb)就是最大傳輸延遲：output delay max = Tdata(pcb) - Tclk2(pcb) + Tsu
四、保持時間余量分析 Slack(Th)
- Data Require Time(數據要求時間) = Tclk2 + Th(芯片數據保持時間) + Latch edge(接收沿) = Tclk2(Init) + Tclk2(Pcb) + Th + Latch edge(接收沿)
- Data Arrival Time(數據到達時間) = Tclk1 + Tco + Tdata + Launch edge(發送沿) = Tclk1 + Tco + Tdata(Init) + Tdata(Pcb) + Launch edge(發送沿)
- Slack(Th)
- Data Arrival Time(數據到達時間) - Data Require Time(數據要求時間)
- 同樣的，可以算出，最小輸出延遲
- Output delay min = Tdata(pcb) - Tclk2(pcb) - Th
五、綜上所述
- output delay max = Tdata(pcb) - Tclk2(pcb) + Tsu
- Output delay min = Tdata(pcb) - Tclk2(pcb) - Th
如果,PCB板上的數據走線長度與時鍾走線長度一樣，即：(5)->(6) = (1)->(7)
那么，Tdata(pcb) = Tclk2(pcb) - output delay max = Tsu
- Output delay min = -Th
六、步驟
-
設計時鍾約束
-
設計輸出延遲
最大延遲
最小延遲
七、時鍾與數據反向輸出
Tsu
- Data Require Time = Tclk2(Int) - Tsu + Latch Edge
- Data Arrival Time = Tclk1(Pcb) + Tclk1(Int) + Tco + Tdata(Pcb) + Tdata(Int) + Lanch Edge
- Slack(Tsu) = Data Require Time - Data Arrival Time
- Slack(Tsu) = (Tclk2(Int) - Tsu + Latch Edge) - (Tclk1(Pcb) + Tclk1(Int) + Tco + Tdata(Pcb) + Tdata(Int) + Lanch Edge) >= 0
- Tclk2(Int) - Tclk1(Int) -Tco - Tdata(Int) >= (Lanch Edge - Latch Edge) + Tsu + Tclk1(Pcb) + Tdata(Pcb)
- output delay max = Tclk1(Pcb) - Tdata(Pcb) + Tsu
Th
- Data Require Time = Tclk2(Int) + Th + Latch Edge
- Data Arrival Time = Tclk1(Pcb) + Tclk1(Int) + Tco + Tdata(Pcb) + Tdata(Int) + Lanch Edge
- Slack(Th) = Data Arrival Time - Data Require Time
- Slack(Th) = (Tclk1(Pcb) + Tclk1(Int) + Tco + Tdata(Pcb) + Tdata(Int) + Lanch Edge) - (Tclk2(Int) + Th + Latch Edge) >= 0
- (Lanch Edge - Latch Edge) + Tclk1(Pcb) + Tdata(Pcb) - Th >= -Tclk1(Int) - Tco - Tdata(Int) + Tclk2(Int)
- output delay min = Tclk1(Pcb) + Tdata(Pcb) - Th
八、IO輸出通用約束模型分析
Tskew = Tclk2 - Tclk1
Tskew(Pcb) = Tclk2(Pcb) - Tclk1(Pcb)
時鍾與數據同向時
Tclk1(Pcb) = 0
- output delay max = Tdata(pcb) - Tclk2(pcb) + Tsu = Tdata(pcb) - (Tclk2(pcb) - Tclk1(Pcb)) + Tsu = Tdata(pcb) - Tskew(Pcb) + Tsu
- output delay min = Tdata(pcb) - Tclk2(pcb) - Th = Tdata(pcb) - (Tclk2(pcb) - Tclk1(Pcb)) - Th = Tdata(pcb) - Tskew(Pcb) - Th
時鍾與數據反向時
Tclk2(Pcb) = 0
- output delay max = Tdata(Pcb) + Tclk1(Pcb) + Tsu = Tdata(Pcb) - (Tclk2(Pcb) - Tclk1(Pcb)) + Tsu = Tdata(pcb) - Tskew(Pcb) + Tsu
- output delay min = Tdata(Pcb) + Tclk1(Pcb) - Th = Tdata(Pcb) -(Tclk2(Pcb) - Tclk1(Pcb)) - Th = Tdata(pcb) - Tskew(Pcb) - Th
綜上，IO輸出約束通用公式為
- output delay max = Tdata(pcb) - Tskew(Pcb) + Tsu
- output delay min = data(pcb) - Tskew(Pcb) - Th