Verilog-數字序列檢測器101 （米利型）

目錄

• 四狀態版
  • 代碼
  • 仿真波形
• 三狀態版
  • 代碼
  • 仿真波形
• 總結
• 移位寄存器版本，並且是米利型的效果，還不帶重疊檢測
  • 代碼
  • 仿真波形

四狀態版

代碼

`timescale 1ns / 1ps

module digit_sequence_detect_mili(
	input clk,
	input rstn,
	input data,
	output detect
    );

localparam IDLE = 2'd0;
localparam S1 = 2'd1;
localparam S10 = 2'd2;
localparam S101 = 2'd3;	 

reg [1:0] state;
reg [1:0] next_state;


always @(posedge clk or negedge rstn) begin
	if(!rstn) state <= IDLE;
	else state <= next_state;
end

always @(*) begin
	case(state)
		IDLE: next_state = data ? S1 : IDLE;  // 狀態轉移用三目運算符
		S1: next_state = data ? S1 : S10;
		S10: next_state = data ? S101 : IDLE;
		S101: next_state = data ? S1 : S10;
		default: next_state = IDLE;
	endcase
end

assign detect = ((state == S10) && (data))? 1'b1 : 1'b0; // 米利狀態機的輸出還與輸入有關

endmodule

仿真波形

三狀態版

代碼

`timescale 1ns / 1ps

module digit_sequence_detect_mili(
	input clk,
	input rstn,
	input data,
	output detect
    );

localparam IDLE = 2'd0;
localparam S1 = 2'd1;
localparam S10 = 2'd2;
localparam S101 = 2'd3;	 

reg [1:0] state;
reg [1:0] next_state;


always @(posedge clk or negedge rstn) begin
	if(!rstn) state <= IDLE;
	else state <= next_state;
end

always @(*) begin
	case(state)
		IDLE: next_state = data ? S1 : IDLE;
		S1: next_state = data ? S1 : S10;
		S10: next_state = data ? S1 : IDLE;  // 在S10狀態下，輸入1直接跳回S1狀態，從而可以節省一個狀態
		//S101: next_state = data ? S1 : S10; 
		default: next_state = IDLE;
	endcase
end

assign detect = ((state == S10) && (data))? 1'b1 : 1'b0;

endmodule

仿真波形

總結

可以看到，三狀態版的仿真波形與四狀態版的仿真波形一致，對於米利型序列檢測器，最少狀態數為序列長度，對於摩爾型序列檢測器，最少狀態數為序列長度加1.
米利型序列檢測器在當周期出檢測結果，摩爾型序列檢測器在下一周期出檢測結果

移位寄存器版本，並且是米利型的效果，還不帶重疊檢測

代碼

reg [2:0] shifter;

always @(posedge clk or negedge rstn) begin
	if(!rstn) shifter <= 0;
	else if(detect) begin
		shifter <= 0;
	end
	else begin
		shifter <= {shifter[1:0],data};
	end
		
end

assign detect = (shifter[1:0] == 2'b10 && data == 1'b1); // 已經檢測到10，下個數據如果是1就置高檢測標志

仿真波形