modelsim的VHDL仿真

前面用過vivado自帶的仿真軟件，我這個仿真新手發現它不能仿真signal信號，所以改用modelsim進行仿真，雖然經歷了一些波折，總歸仿出結果了，下面記錄下仿真過程作為備忘：

首先新建project ，添加主文件.vhd和testbench.vhd,全部編譯，如下圖即是編譯成功：

 

一定要在如下library里點擊仿真，不然可能會出現信號缺失的情況：

然后在work下面找到testbench中的architecture，右擊，simulation：

 

這時自動跳到波形界面，此時在instance單元左擊testbench就會在objects看到輸入輸出信號，但是沒有內部型號：

 

 左擊instance中uut模塊就可以看到主文件內的signal信號和定義的各種變量常量：

 

 這時，就可以將需要的信號抓到觀測區，選中需要的信號，右擊，add wave：

 

 帶觀測區如下：

 

 這時就是最后一步了，設置仿真時間點擊顯示，就是點擊仿真時間右邊的那個run（開始忘記這一步，發現總是看不見波形，惱火！），其實直接在命令行輸入run也是可以的。

 

此時就可以看到波形咯！

 最后放下我兩個程序吧，一個mystate，一個mystate_tb是狀態機學習的程序：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--------------------------------------------------------
ENTITY mystate IS
    PORT(A,clk,rst: IN STD_LOGIC;
         output_state: OUT STD_LOGIC);
END mystate;
--------------------------------------------------------
ARCHITECTURE rtl OF mystate IS
    CONSTANT s0: STD_LOGIC_VECTOR(1 downto 0):="00";
    CONSTANT s1: STD_LOGIC_VECTOR(1 DOWNTO 0):="01";
    CONSTANT S2: STD_LOGIC_VECTOR(1 DOWNTO 0):="11";
    SIGNAL current_state: STD_LOGIC_VECTOR(1 DOWNTO 0);
    SIGNAL next_state: STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
    PROCESS(clk,rst)
    BEGIN
        IF(rst='1') THEN
            current_state<=s0;
            ELSIF(clk'EVENT AND clk='1') THEN
                current_state<=next_state;
        END IF;
    END PROCESS;
    
    PROCESS(current_state,A)
    BEGIN
        CASE current_state IS
            WHEN s0=>
                IF(A='0') THEN
                    next_state<=s0;
                ELSE
                    next_state<=s1;
                END IF;
            WHEN s1=>
                IF(A='0') THEN
                    next_state<=s2;
                ELSE
                    next_state<=s1;
                END IF;
            WHEN s2=>next_state<=s0;
            WHEN OTHERS=>NULL;
        END CASE;
    END PROCESS;

    PROCESS(current_state,A)
    BEGIN
        CASE current_state IS
            WHEN s0=>
                IF(A='0') THEN
                    output_state<='0';
                ELSE
                    output_state<='1';
                END IF;
            WHEN s1=>
                IF(A='0') THEN
                    output_state<='1';
                ELSE
                    output_state<='0';
                END IF;
            WHEN s2=>
                IF(A='0') THEN
                    output_state<='0';
                ELSE
                    output_state<='1';
                END IF;
            WHEN OTHERS=>NULL;
        END CASE;
    END PROCESS;
    
END rtl;

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity mystate_tb is
end;

architecture bench of mystate_tb is

  component mystate
      PORT(A,clk,rst: IN STD_LOGIC;
           output_state: OUT STD_LOGIC
           );
  end component;

  signal A,clk,rst: STD_LOGIC;
  signal output_state: STD_LOGIC;

  constant clock_period: time := 10 ns;
  signal stop_the_clock: boolean;

begin

  uut: mystate port map ( A            => A,
                          clk          => clk,
                          rst          => rst,
                          output_state => output_state 
                        );

  stimulus: process
  begin
  
   A<='0';
   wait for 20ns;
   A<='1';
   wait for 20ns;
    A<='0';
   wait for 20ns;
    A<='0';
   wait;

    stop_the_clock <= true;
    wait;
  end process;

  clocking: process
  begin
    while not stop_the_clock loop
      clk <= '0', '1' after clock_period / 2;
      wait for clock_period;
    end loop;
    wait;
  end process;
resetmy:PROCESS
   BEGIN
     rst<='1';
     wait for 30 ns;
     rst<='0';
     wait;
   END PROCESS;
end;