W25QXX系列芯片手冊學習
概況
The W25Q128BV (8M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1μA for power-down.
The W25Q128BV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128BV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.)
The W25Q128BV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual Output and 280MHz (70MHz x 4) for Quad SPI when using the Fast Read Quad SPI instructions. These transfer rates can out perform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top, bottom or complement array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number.
W25Q128BV為空間、引腳和電源受限的系統提供存儲的解決方案，25Q系列的flash都是NOR Flash，W25Q128BV可編程的頁(page)有65536個，每個頁256字節（4個頁1KB），一次可以訪問256字節（一個頁）。
頁可以一組一組的擦除，每組可以含有16/128/256個頁，或者是整片擦除。擦16個頁被稱作扇區擦除(sector erase)，擦128個頁被稱作塊擦除(block erase)。根據定義，可編程的page有65536個，16個page是一個sector，256個page是一個block，因此可被索引到的sector有4096個，block有256個。
通信協議為標准SPI協議，引腳復用可以選擇雙路或4路SPI通信，同時最大時鍾也有不同。另外還包括一個Hold腳，寫保護腳，同時有一個64bit,8字節的唯一設備序列號。
關於SPI
常見的SPI通信實現一般包括4根線，CLK,CS,MOSI,MISO，協議的原理比較簡單，其實就是在時鍾的不同邊沿處選擇輸入還是輸出，當選擇是輸入的時候，數據線要有保持數據的能力；當輸出的時候，數據線要能夠改變電平來輸出數據。
用一張圖來說明（隨便找的，不一定對）
根據CLK的極性（兩個采樣沿，空閑時電平是高是低），SPI可以分4種工作模式（CLK的排列組合），這里不介紹工作模式（因為圖也不一定對）。主要說一下以下幾點
- 無論是哪種模式，當采集的時候，電平要保持住，不采集的時候，電平可以改變
- 由於CLK的存在，采樣和變更電平的是要遵守時序的
- 這里注意一下SDI和SDO的流向，當SCLK上升沿時，對主機M是輸入，采樣階段，因此SDI數據是保持住的，當SCLK下降沿時，對主機M是輸出，SDO是保持狀態
從上面的介紹可以看出，實現SPI最少可以只需要2根線，即SCL和SDA，由SCL提供時序，SDA用來傳輸數據。這時由於一個時鍾周期內只能提供兩個邊沿，因此只能是一個邊沿采樣，一個邊沿輸出（改變電平）。
回到W25Q128上：
根據手冊的引腳定義可以看出有3種使用方式（圖片標注有誤，以文字為准）：
- DI和DO構成SPI的IO線，一收一發，同時寫保護和保持腳都能夠按原來的功能使用
- DI和DO構成SPI的IO線，但是均作為單路雙向IO，實現雙路SPI的發送
- HOLD和WP腳被復用至IO腳，這樣有4個雙向IO腳，實現4路SPI的發送
這里盡管說支持雙路和4路SPI，但是由於沒有讀控和寫控，因此其實只能提供被讀取的功能，也就是說Flash芯片被設置為S設備而只能被讀寫而不能發起讀寫。
我們跳過文檔部分關於封裝和引腳定義部分的內容，進入引腳描述部分。
引腳描述
這里主要介紹幾個引腳，IO，寫保護，保持。IO這里由於支持3種多路SPI方式，因此當采用標准SPI時，DI腳輸入，在CLK上升沿寫入地址或數據，DO在CLK下降沿輸出。
寫保護和保持均由寄存器2控制，當寄存器2設置為雙路或4路時，寫保護和保持的原有功能失效。
模塊框圖
功能描述
SPI標准模式
The W25Q128BV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0, 0) and 3 (1, 1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
DI可以寫指令，地址或數據，DO可以讀數據或狀態。工作模式可以是模式0或模式3
SPI雙路模式
The W25Q128BV supports Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.
雙路模式在3Bh，BBh指令執行后使用，執行后DI和DO將被設置成雙向IO的IO0和IO1。
SPI四路模式
The W25Q128BV supports Quad SPI operation when using the “Fast Read Quad Output (6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O (E3h)” instructions. These instructions allow data to be transferred to or from the device six to eight times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
類似雙路，執行6B,EB,E7,E3指令后可以使用4路模式，引腳被復用。四路模式需要狀態寄存器2的QE位保持有效不發生改變
其他功能如保持和寫保護這里暫時跳過。
狀態寄存器和指令
狀態寄存器1和狀態寄存器2的位定義如圖：
具體的每一位的含義在手冊中已經寫明，這里說一下這兩個寄存器如何訪問（用指令來交互的格式）：
The instruction set of the W25Q128BV consists of thirty five basic instructions that are fully controlled through the SPI bus (see Instruction Set table1-3). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 4 through 37. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed.
從SPI發送的第一個字節就是指令的指令碼，根據描述，指令的總長度是變長的，即指令碼后面可能跟隨着：地址、數據、占位等等。
指令如下表（部分）：
BYTE1的位置表示發送的第一個字節，可以看出大部分都是只發一個字節，05H和35H發送后會收到1個字節的返回值，而01H，02H...D8H發送的數據長度均大於1個字節。注意讀寫地址線只有24根，即可索引的地址范圍為0x00000000-0x00FFFFFF，即16M，剛好索引到全部地址范圍。
注意02H，之前說到過，手冊上寫的一次編程大小是一頁，即256字節，所以02的指令描述那里其實是BTYE5后面要跟256個字節，這里可能是沒有標明。這一點在后面的時序圖中也可以得到印證：
這里吐槽一下，畫時序圖固然有助於硬件工程師設計，但是應該同時配一組協議格式說明表格一類的文檔，便於軟件開發，讀時序對於簡單協議尚能接受，但是對於這種整字節操作應該直接用字節表示更清晰些。后面全部都是指令協議的定義和說明，就不介紹了。