參考：PG201 AXI DMA v7.1 AXI IP核
功能：一旦處理器配置好傳輸方式之后，DMA可以自己完成內存數據的搬進或者搬出，而不需要處理器的介入。如果使用方法得當，DMA可以顯著地提高系統性能。
AXIDMA IP有6個接口，S_AXI_LITE是ARM配置dma寄存器的接口，M_AXI_SG是從（往）存儲器加載（上傳）buffer descriptor的接口，剩下4個構成兩對接口，S2MM和MM2S表示數據的方向，AXI是存儲器一側的接口，AXIS是FPGA一側的接口。AXIDMA IP和ARM自帶的DMA是很像的，只不過不具備從存儲器到存儲器的功能，當然啦如果將S2MM和MM2S的AXIS接口直接連接也是可以實現的。
AXIDMA工作模式分為兩種，分別是Direct Register Mode和Scatter/Gather Mode。Direct Register Mode具備DMA的基本功能，除了控制寄存器和狀態寄存器之外，給出源（目的）地址和傳輸長度之后就可以開啟一次傳輸了。Direct Register Mode的特點（也是缺點）是配置完一次寄存器之后只能完成存儲器連續地址空間的讀寫，如果有需求往不同地址空間搬運數據的話，那就需要重新配置寄存器開啟一次新的傳輸。
鑒於Direct Register Mode的不足，發展出了Scatter/Gather Mode，其工作方式要復雜得多。Scatter/Gather Mode把關於傳輸的基本參數（比如起始地址、傳輸長度、包信息等）存儲在存儲器中，一套參數稱之為Buffer Descriptor（簡稱BD），在工作過程中通過上面提到的SG接口來加載BD並且更新BD中的狀態。從圖3可以看出，Scatter/Gather Mode下的寄存器列表中沒有了Address、Length相關的寄存器了，取而代之的是CURDESC、TAILDESC。
MM2S_DMACR
AXIDMA啟動后，首先從CURDESC指定的位置加載BD，完成當前BD的傳輸任務后根據BD鏈條找到下一個BD，依次完成BD指定的傳輸，直到遇到TAILDESC指定的BD才停止。
Multichannel DMA：在Scatter/Gather Mode下S2MM和MM2S都支持多個通道，Direct Register Mode不支持多通道。如圖5所示，多通道相比非多通道，BD中增加了TID和TDEST，用來區分不同的通道。
Data Cache：從圖9中可以看出，在ZYNQ內部ARM CPU與DDR3之間存在兩級緩存區，分別是L1 I/D Cache和L2 Cache，它們都是32-byte line size。Data Cache的使用帶來了一個問題，DMA和CPU都與DDR3有數據往來，可CPU的Cache是不知道DMA對DDR3的數據讀寫過程的，也就是說CPU得到的數據很可能是”假的“，這就是著名的Cache一致性問題。解決該問題的辦法是在程序中使用flush函數（invalid函數）及時將Cache的數據寫入到DDR3（從DDR3讀取數據到Cache），也就是說要避免該問題就只能靠我們自己了。
Programming Sequence ：
Direct Register Mode(Simple DMA)A DMA operation for the MM2S channel is set up and started by the following sequence ：
1. Start the MM2S channel running by setting the run/stop bit to 1 (MM2S_DMACR.RS =
1). The halted bit (DMASR.Halted) should deassert indicating the MM2S channel is
running
2. If desired, enable interrupts by writing a 1 to MM2S_DMACR.IOC_IrqEn and
MM2S_DMACR.Err_IrqEn. The delay interrupt, delay count, and threshold count are not
used when the AXI DMA is configured for Direct Register Mode.
3. Write a valid source address to the MM2S_SA register. If AXI DMA is configured for an
address space greater than 32, then program the MM2S_SA MSB register. If the AXI DMA
is not configured for Data Re-Alignment, then a valid address must be aligned or
undefined results occur. What is considered aligned or unaligned is based on the stream
data width. When AXI_DMA is configured in Micro Mode, it is your responsibility to
specify the correct address. Micro DMA does not take care of the 4K boundary.
For example, if Memory Map Data Width = 32, data is aligned if it is located at word
offsets (32-bit offset), that is 0x0, 0x4, 0x8, 0xC, and so forth. If DRE is enabled and
Streaming Data Width < 128, then the Source Addresses can be of any byte offset.
4. Write the number of bytes to transfer in the MM2S_LENGTH register. A value of zero
written has no effect. A non-zero value causes the MM2S_LENGTH number of bytes to
be read on the MM2S AXI4 interface and transmitted out of the MM2S AXI4-Stream
interface. The MM2S_LENGTH register must be written last. All other MM2S registers
can be written in any order. In the case of Micro DMA, this value cannot exceed
[Burst_length * (Memory Mapped Data Width)/8].
A DMA operation for the S2MM channel is set up and started by the following sequence:
1. Start the S2MM channel running by setting the run/stop bit to 1 (S2MM_DMACR.RS =
1). The halted bit (DMASR.Halted) should deassert indicating the S2MM channel is
running.
2. If desired, enable interrupts by writing a 1 to S2MM_DMACR.IOC_IrqEn and
S2MM_DMACR.Err_IrqEn. The delay interrupt, delay count, and threshold count are not
used when the AXI DMA is configured for Direct Register Mode.
3. Write a valid destination address to the S2MM_DA register. If AXI DMA is configured for
an address space greater than 32, program the S2MM_DA MSB register.
4. If the AXI DMA is not configured for Data Re-Alignment then a valid address must be
aligned or undefined results occur. What is considered aligned or unaligned is based on
the stream data width
5. Write the length in bytes of the receive buffer in the S2MM_LENGTH register. A value of
zero has no effect. A non-zero value causes a write on the S2MM AXI4 interface of the
number of bytes received on the S2MM AXI4-Stream interface. A value greater than or
equal to the largest received packet must be written to S2MM_LENGTH. A receive buffer
length value that is less than the number of bytes received produces undefined results.
When AXI DMA is configured in Micro mode, this value should exactly match the bytes
received on the S2MM AXI4-Stream interface. The S2MM_LENGTH register must be
written last. All other S2MM registers can be written in any order