物理綜合：timing_path&path_group

關於path and path group

• 本文針對常見的path和pathgroup 問題,做深入的分析和總結

• path 和path group 屬於時序設計中的基本問題,屬於必須掌握的知識點

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Design and library objects

• Ports Versus Pins

•   ‘Ports’ are the inputs and outputs of the current design

•   ‘Pins’ are the inputs and outputs of any cell that isinstantiated in the current design

PathDelay

• Path Delays are Based on Cell + Net Delays 

• PathDelay

•   Path delay section

PathDelay

•  Define setup timing constraints for all paths within asequential design

•     All input logic paths (startingat input ports)

•    The internal (register to register) paths

•    All output paths (ending at output ports)

•    Starting at input ports and ending at output ports 

• Static timing analysis Fundamentals

•   Static Timing Analysis can determine if a circuit meetstiming constraints without dynamic simulation

•  This involves three main steps:

•      design is broken down into timingpaths

•      The delay of each path is calculated

•      All path delays are checked against timing constraints

Static timing analysis Fundamentals

•   Grouping of Timing Paths into Path Groups

•      report_path_group

•      Paths are grouped by the clocks controlling their endpoints

Static timing analysis Fundamentals

•   Timing Paths and Group Paths

•      How many timing paths are there? 

•      How many path groups are there?  

Path and path group總結

•   Path and path group 屬於時序中的基礎問題

•   Path group 要盡量做到最簡化

•   一定要學會畫波形圖和時序圖,正確區分path和pathgroup,做到全覆蓋

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