使用FPGA開發板驅動VGA顯示器

1. 本次使用的是cyclone4開發板，先看下原理圖，因為右邊的RGB應該是模擬信號量，但是本次例程只接了3根線，那就是說顏色只有8種。

2. 代碼，輸出信號有R,G,B三色，就是上圖右邊的，行同步信號（掃描完一行），場同步信號。VGA收發雙方沒有時鍾信號做同步，但是通常會約定發送方有一個基本的時鍾，行同步信號HSYNC在每行開始的時候產生一個固定寬度的高脈沖。場同步信號VSYNC在每幀（即一次全屏的圖像）開始的時候產生一個固定寬度的高脈沖。我對關鍵的信號，畫了時序圖，發現不是很理解程序的機制。

module VGA(
   clock,
   switch,
   disp_RGB,
   hsync,
   vsync
);
input  clock;     //系統輸入時鍾 50MHz
input  [1:0]switch;
output [2:0]disp_RGB;    //VGA數據輸出
output  hsync;     //VGA行同步信號
output  vsync;     //VGA場同步信號

reg [9:0] hcount;     //VGA行掃描計數器
reg [9:0]   vcount;     //VGA場掃描計數器
reg [2:0]   data;
reg [2:0]  h_dat;
reg [2:0]   v_dat;

//reg [9:0]   timer;

reg   flag;
wire  hcount_ov;
wire  vcount_ov;
wire  dat_act;
wire  hsync;
wire   vsync;
reg  vga_clk;
//VGA行、場掃描時序參數表
parameter hsync_end   = 10'd95,
   hdat_begin  = 10'd143,
   hdat_end  = 10'd783,
   hpixel_end  = 10'd799,
   vsync_end  = 10'd1,
   vdat_begin  = 10'd34,
   vdat_end  = 10'd514,
   vline_end  = 10'd524;


always @(posedge clock)
begin
 vga_clk = ~vga_clk;
end

//************************VGA驅動部分******************************* 
//行掃描     
always @(posedge vga_clk)
begin
 if (hcount_ov)
  hcount <= 10'd0;
 else
  hcount <= hcount + 10'd1;
end
assign hcount_ov = (hcount == hpixel_end);
//場掃描
always @(posedge vga_clk)
begin
 if (hcount_ov)
 begin
  if (vcount_ov)
   vcount <= 10'd0;
  else
   vcount <= vcount + 10'd1;
 end
end
assign  vcount_ov = (vcount == vline_end);
//數據、同步信號輸
assign dat_act =    ((hcount >= hdat_begin) && (hcount < hdat_end))
     && ((vcount >= vdat_begin) && (vcount < vdat_end));
assign hsync = (hcount > hsync_end);
assign vsync = (vcount > vsync_end);
assign disp_RGB = (dat_act) ?  data : 3'h00;       

//************************顯示數據處理部分******************************* 
//圖片顯示延時計數器
/*always @(posedge vga_clk)
begin
 flag <= vcount_ov;
 if(vcount_ov && ~flag)
  timer <= timer + 1'b1;
end
*/

always @(posedge vga_clk)
begin
 case(switch[1:0])
  2'd0: data <= h_dat;      //選擇橫彩條
  2'd1: data <= v_dat;      //選擇豎彩條
  2'd2: data <= (v_dat ^ h_dat); //產生棋盤格
  2'd3: data <= (v_dat ~^ h_dat); //產生棋盤格
 endcase
end

always @(posedge vga_clk)  //產生豎彩條
begin
 if(hcount < 223)
  v_dat <= 3'h7;      //白   
 else if(hcount < 303)
  v_dat <= 3'h6;   //黃
 else if(hcount < 383)
  v_dat <= 3'h5;   //青
 else if(hcount < 463)
  v_dat <= 3'h4;    //綠
 else if(hcount < 543)
  v_dat <= 3'h3;   //紫
 else if(hcount < 623)
  v_dat <= 3'h2;   //紅
 else if(hcount < 703)
  v_dat <= 3'h1;   //藍
 else 
  v_dat <= 3'h0;   //黑
end

always @(posedge vga_clk)  //產生橫彩條
begin
 if(vcount < 94)
  h_dat <= 3'h7;        //白
 else if(vcount < 154)
  h_dat <= 3'h6;   //黃
 else if(vcount < 214)
  h_dat <= 3'h5;   //青
 else if(vcount < 274)
  h_dat <= 3'h4;    //綠
 else if(vcount < 334)
  h_dat <= 3'h3;   //紫
 else if(vcount < 394)
  h_dat <= 3'h2;   //紅
 else if(vcount < 454)
  h_dat <= 3'h1;   //藍
 else 
  h_dat <= 3'h0;   //黑
end

endmodule

3. 用quartus軟件綜合一下工程，燒寫，插上顯示器的VGA接口，可以看到顯示器顯示的8種顏色。