在ISE平台上實現跑馬燈並燒錄到FPGA VIRTEX7板子上

首先新建工程文件File-New Project

我的FPGA板子型號如下：

 建好工程文件后編寫代碼：在紅色區域右鍵New Source

 

 定義引腳：因為V7時鍾為差分時鍾，所以需要兩個時鍾信號clk_in_p、clk_in_n

 編輯led.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 22:33:25 01/15/2018 
// Design Name: 
// Module Name: led 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module led(
input clk_in_p,
input clk_in_n,
input reset,
output [3:0] led_out
);

reg [26:0] counter;

wire clk;
IBUFGDS clkgen(.O(clk),.I(clk_in_p),.IB(clk_in_n));

always @(posedge clk)
if (reset)
counter <= 0;
else 
counter <= counter + 1;

assign led_out = counter[26:23]; //用於燒寫
//assign led_out = counter[3:0]; //用於仿真

endmodule

接下來進行仿真，編輯test.v

test.v如下

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date: 11:06:12 01/16/2018
// Design Name: led
// Module Name: C:/Users/dell/Desktop/led/led/test.v
// Project Name: led
// Target Device: 
// Tool versions: 
// Description: 
//
// Verilog Test Fixture created by ISE for module: led
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test;

// Inputs
reg clk_in_p;
reg clk_in_n;
reg reset;

// Outputs
wire [3:0] led_out;

parameter PERIOD = 10;

// Instantiate the Unit Under Test (UUT)
led uut (
.clk_in_p(clk_in_p), 
.clk_in_n(clk_in_n), 
.reset(reset), 
.led_out(led_out)
);

always begin

#(PERIOD/2) clk_in_p = 1'b1;clk_in_n = 1'b0;
#(PERIOD/2) clk_in_p = 1'b0;clk_in_n = 1'b1;
end

initial begin
// Initialize Inputs
clk_in_p = 1'b0;
clk_in_n = 1'b0;
reset = 1;

// Wait 100 ns for global reset to finish
#500;

// Add stimulus here
reset = 0;

end

endmodule

編輯完test.v之后，點擊紅色區域，實現仿真

仿真頁面如下

編寫約束文件

NET "clk_in_p" LOC = E19;
NET "clk_in_n" LOC = E18;
NET "led_out[0]" LOC = AM39;
NET "led_out[1]" LOC = AN39;
NET "led_out[2]" LOC = AR37;
NET "led_out[3]" LOC = AT37;
NET "reset" LOC = AV40;

NET "clk_in_p" IOSTANDARD = LVDS;
NET "clk_in_n" IOSTANDARD = LVDS;
NET "led_out[0]" IOSTANDARD = LVCMOS18;
NET "led_out[1]" IOSTANDARD = LVCMOS18;
NET "led_out[2]" IOSTANDARD = LVCMOS18;
NET "led_out[3]" IOSTANDARD = LVCMOS18;
NET "reset" IOSTANDARD = LVCMOS18;

編譯通過

實現燒寫：紅色區域——run

 

 

 

 

 

 

 

 右鍵： program