二進制碼轉BCD碼的verilog實現

二進制碼轉BCD碼的實現可以通過一個特殊的4位移位處理來實現，該實現機制是，判斷該移位器中的數字是否大於4,是的話則加3再左移，否則直接左移。可以這樣考慮，在BCD碼中，如果一個數大於9,則需要減去10然后想前進一位，因而可以通過加3再左移來實現，即先調整再移位，這樣方便實現。

假定輸入二進制碼為9位，輸出為12位。

實現代碼

module bin2bcd(
    input wire clk, nrst,
    input wire start,
    input wire [8:0] bin,
    output reg [11:0] bcd,
    output reg valid
    );
    
    reg [8:0] bin_in;
    reg op;
    reg [3:0] cnt;

    always @(posedge clk or negedge nrst) begin
    if(nrst == 0)
            bin_in <= 0;
    else if(start)
        bin_in <= bin;
    end
    
    always @(posedge clk or negedge nrst) begin
        if(nrst == 0)
            op <= 0;
        else if(start)
            op <= 1;
        else if(cnt == 9 - 1)
            op <= 0;
    end

    always @(posedge clk or negedge nrst) begin
        if(nrst == 0)
            cnt <= 0;
        else if(op)
            cnt <= cnt + 1'b1;
        else
            cnt <= 0;
    end

    function [3:0] fout(input reg [3:0] fin);
        fout = (fin > 4) ? fin + 4'd3 : fin;
    endfunction

    always @(posedge clk or negedge nrst) begin
        if(nrst == 0)
            bcd <= 0;
        else if(op) begin
            bcd[0] <= bin_in[8-cnt];
            bcd[4:1] <= fout(bcd[3:0]);
            bcd[8:5] <= fout(bcd[7:4]);
            bcd[11:9] <= fout(bcd[11:8]);
          end
        else
            bcd <= 0;
    end

    always @(posedge clk or negedge nrst) begin
    if(nrst == 0)
        valid <= 0;
    else if(cnt == 9 - 1)
        valid <= 1;
    else
        valid <= 0;    
    end
endmodule

測試平台代碼

`timescale 1ns/10ps

module bin2bcd_tb;

    // parameter
    localparam T = 20;    

    // declaration
    reg clk, nrst;
    reg [8:0] bin;
    reg start;
    wire [11:0] bcd;
    wire valid;

    // instantiation
    bin2bcd uut(
        .clk    (clk    ),
        .nrst   (nrst   ),
          .start        (start    ),
        .bin    (bin    ),
        .bcd    (bcd    ),
          .valid    (valid    )
    );

    // clock
    initial begin
        clk = 1;
        forever # (T/2) clk = ~clk;
    end

    // reset
    initial begin
        nrst = 1;
        @(negedge clk) nrst = 0;
        @(negedge clk) nrst = 1;
    end

    // test 4 instance
    initial begin
        // initiate
        bin = 0;
        start = 0;

        // wait for reset
        repeat(2) @(negedge clk);

        // test 0
        @(negedge clk) 
            bin = 0;
            start = 1;
        @(negedge clk)
            bin = 0;
            start = 0;
        repeat(15) @(negedge clk);


        // test 0b1001
        @(negedge clk) 
            bin = 9'b1001;
            start = 1;
        @(negedge clk)
            bin = 0;
            start = 0;
        repeat(15) @(negedge clk);


        // test 0b1111
        @(negedge clk) 
            bin = 9'b1111;
            start = 1;
        @(negedge clk)
            bin = 0;
            start = 0;
        repeat(15) @(negedge clk);

        // test 0b1_0000
        @(negedge clk) 
            bin = 9'b1_0000;
            start = 1;
        @(negedge clk)
            bin = 0;
            start = 0;
        repeat(15) @(negedge clk);

        // test 0b1_1111_1111
        @(negedge clk) 
            bin = 9'b1_1111_1111;
            start = 1;
        @(negedge clk)
            bin = 0;
            start = 0;
        repeat(15) @(negedge clk);

        // stop
        $stop;
    end
endmodule

參考圖書《基於Nios II的嵌入數SoPC系統設計與Verilog開發實例》