altera DDR2 ip使用筆記之IP核生成

IP核生成

Quartus生成DDR2 ip流程如下：

點擊菜單欄的Tools->MegaWizard Plug-In Manager，彈出

 選擇IP類型，保持路徑即文件名等，如下圖

 點擊next，按下圖設置：輸入時鍾50Mhz，DDR驅動時鍾150Mhz，Full rate模式，位寬32Bit，器件選擇MT47H64M16，與所使用的FPGA開發板一致。

 點next，選擇默認即可

 依舊默認

 設置MaxBurstCount為64，

 選擇產生仿真模型

 最后點擊finish完成

 等待gereration

 完成

 以下是log信息

Info: Generating the Example Design.
Info: Generating the Pin Planner file.
Info: Generating the Synopsys Design Constraints file for the example top level.
Info: Generating the Synopsys Design Constraints file.
Info: Generating the Timing Report script.
Info: Generating the ALTPLL Megafunction instance.
Info: Generating the ALTMEMPHY Megafunction instance.
Info: Generating the Functional Simulation Model for ALTMEMPHY
Info: Before compiling your variation in Quartus II, you should follow these steps:
Info: - Enable TimeQuest under Settings, Timing Analysis Settings.
Info: - Add the alt_ddr2_ip_phy_ddr_timing.sdc file to your Quartus II project.
Info: - Add I/O Standard assignments by running the alt_ddr2_ip_pin_assignments.tcl script.
Info: - Set the Default I/O standard to match the memory interface I/O standard setting.
Info: - Turn on Optimize multi-corner timing in the Quartus II Fitter Settings.
Info: - Please make sure that address/command pins are placed on the same edge as the CK/CK# pins.
Info: - Set the top level entity of the project to alt_ddr2_ip_example_top.
Info: See the User Guide for more details.