systemverilog語法


1. assertion

assertion相關的 |->和 |=>的區別:

sequence_expr |-> property_expr : the end of sequence_expr is the start of property_expr.

sequence_expr |=> property_expr : the start of property_expr is 1 clock tick after the end of sequence_expr.

 

##0 indicates the beginning of the second sequence is the end of the first sequence.

##1 indicates the beginning of the second sequence is 1 clock tick later than the end of the first sequence.

seq1 ##[m:n] seq2 means seq2 must be true between m ~ n clock tick later than seq 1 is true.

$ means t the end of simulation.

 

intersect: seq1 intersect seq2, means seq1 and seq2 match at the same time.

throughout: exp1 throughout seq2, means exp1 must be true when seq2 is matched.

within: seq1 within seq2, means seq 1 must be matched during the period when seq2 is true.

2. rand

rand constraint

class A;

  rand v;

  constraint c_v{ v inside {0,1};}

endclass

A a;

a.c_v.constraint_mode(0); // 0-disable the rand constraint c_v.

 

%d 以及 %D 以十進制格式輸出

%b 以及 %B 以二進制格式輸出

%o 以及 %O 以八進制格式輸出

%h 以及 %H 以十六進制格式輸出

%s 以及 %S 以字符串格式輸出

%c 以及 %C 以ASCII碼格式輸出

%v 以及 %V 輸出線網類型變量的強度

%m 以及 %M 輸出層次名

%t 以及 %T 以當前時間格式輸出

%e 以及 %E 以指數表示方式輸出實數(real型)

%f 以及 %F 以十進制數表示方式輸出實數(real型)

%g 以及 %G 以十進制數或者以指數表示方式輸出實數


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