1、單次轉換模式
通過配置“模式寄存器的MD2、MD1、MD0為001”，便可啟動單次轉換。
流程“上電 -》 單次轉換 -》 省電模式 ” ， 片內振盪上電需要大約1ms。
單次轉換的時序圖：
數字的含義：0x08 ：表示后面的數字是用來設置mode register的；
0x280060：用來設置單次轉換的參數；
0x58：讀數據寄存器；
DATA：就是ADC對應通道采集的值。
完成轉換后，DOUT/RDY變成低電平。從數據寄存器中讀取數據字后，DOUT/RDY變為高電平。如果CS為低電平，DOUT/RDY將保持高電平，直到又啟動並完成一次轉換為止。如果需要，即使DOUT/RDY已變為高電平，也可以多次讀取數據寄存器。
2、多通道的單次轉換
如果使能了多個通道，ADC將依次選擇各使能通道，並在該通道上執行轉換。轉換啟動后，DOUT/RDY變為高電平並保持該狀態，直到有有效結果可用為止。轉換結果一旦可用，DOUT/RDY便會變成低電平。然后ADC選擇下一個通道並開始轉換。在執行下一個轉換過程中，用戶可以讀取當前的轉換結果。下一轉換一旦完成，數據寄存器便會更新。用戶讀取轉換結果時間是有限的。ADC在各選擇通道上均完成一次轉換后，便會返回省電模式。
如果模式寄存器的DAT_STA位設置為1 ，則每次執行數據讀取時，狀態寄存器的內容將與轉換結果一同輸出。狀態寄存器的四個LSB指示轉換對應的通道。
3、連續轉換模式
連續轉換模式是上電默認模式。
AD7190連續轉換，每次轉換完成時，狀態機寄存器中的RDY位變為低電平。如果CS為低電平，則當一次轉換完成時，DOUT/RDY將變為低電平。
若要讀取轉換結果，用戶需要寫入通信寄存器，指示下一操作為讀取數據寄存器。從數據寄存器中讀取數據字后，DOUT/RDY將變為高電平。如需要，用戶可以多次讀取該寄存器。但是，用戶必須確保在下一次轉換完成時，對數據寄存器的訪問已經結束，否則新轉換字將丟失。
如果使能了多個通道，ADC將連續循環選擇各使能通道，每次循環均會在每個通道上執行一次轉換。一旦獲得轉換結果，就會立即更新數據寄存器。每次轉換結果可用時，DOUT/RDY將變為低電平。然后，用戶可以讀取轉換結果，同時ADC在下一個使能通道上執行轉換。
如果模式寄存器的DAT_STA位設置為1 ，則每次執行數據讀取時，狀態寄存器的內容將與轉換結果一同輸出。狀態寄存器的四個LSB指示轉換對應的通道。
4、連續讀取
可以對AD7190記性配置，使得每次轉換完成時，轉換結果會自動置於DOUT/RDY線上，而無需每次寫入通信寄存器以訪問數據。
將0x5C（01011100）寫入通信寄存器后，用戶只需要提供適當的SCLK周期數，這樣當轉換完成時，轉換字便會自動置於DOUT/RDY線路上。ADC應配置為連續轉換模式。
若要退出連續讀取模式，必須在RDY引腳為低電平時將指令0x58（01011000）寫入通信寄存器。在連續讀取模式下，ADC會監控DIN線路上的活動，以便能接收到指令以后以退出連續讀取模式。
此外，如果DIN上出現40個連續1，ADC將復位。因此在連續讀取模式下，DIN應保持低電平，直到有指令要寫入器件。
如果使能了多個通道，ADC將連續依次選擇各使能通道，並在所選擇通道上執行一次轉換。當一個轉換結果可用時，DOUT/RDY便會變為低電平。當用戶施加足夠多的SCLK脈沖時，數據便會自動置於DOUT/RDY引腳上。
如果模式寄存器的DAT_STA位設置為1 ，則每次執行數據讀取時，狀態寄存器的內容將與轉換結果一同輸出。狀態寄存器的四個LSB指示轉換對應的通道。
| 類型 | 濾波類型 | 建立時間 | 轉換時間 |
| 禁止斬波 | sinc3 | Tsettle = 3/Fadc | Fadc = Fclk/(1024 * FS[9:0]) |
| sinc4 | Tsettle = 4/Fadc | ||
| 使能斬波 | sinc3 | Tsettle = 2/Fadc | Fadc = Fclk/(3*1024 * FS[9:0]) |
| sinc4 | Fadc = Fclk/(4*1024 * FS[9:0]) |
5、P0 P1 P2 P3腳的作用
AD7190 通過外界多路復用器（如：4選1,8選1）在選擇AD7190采集哪個通道。
6、關於AD7190采集通道的幾點問答
1、What is the sequence of events when switching between channels for the AD719x when the sequencer is disabled and continuous conversion mode is selected?
（對於AD719x來說，當序列不是使能時，並且選擇了連續轉換模式，如何切換通道？）
轉換器開頭寫入通信寄存器的每個序列的事件將會指定下一個操作。
例如使用 AD7190/AD7192，通道切換操作的順序如下是 （通道 AIN1_AIN2 和 AIN3_AIN4 ）。
進行通道切換的條件是：兩個通道的工作條件都是 50 赫茲輸出數據速率；內部的主時鍾；增益 = 1；緩沖區對雙極模式;應用 REFIN1(+) 和 REFIN1(–) 之間的外部引用是 ADC 的參考源；AD719x 是 24 位部分。
每個序列的事件與此轉換器開頭寫入通信寄存器來指定要執行下一個操作。完成指定的操作時，界面默認為等待下一個指令。
1、Write 0x8 to communications register: This specifies that the next operation is a write to the mode register.
2、Write 0x080060 to mode register: This configures the AD719x for an output data rate of 50 Hz and the internal clock is used.
3、Write 0x10 to communications register: This specifies that the next operation is a write to the configuration register.
4、Write 0x000110 to configuration register: This configures the AD719x for the above gain, polarity, and reference source and selects Channels AIN1–AIN.
5、Write 0x58 to the communications register: This specifies that the next operation is a write of the data register.
6、Poll DOUT/RDY: Poll the DOUT/RDY pin to determine if valid data is available in the data register. When DOUT/RDY goes low, apply 24 serial clocks to clock the data from the ADC. A read should not be initiated when DOUT/RDY is high.
7、Write 0x10 to communications register: This specifies that the next operation is a write to the configuration register
8、Write 0x000210 to configuration register: This configures the AD719x for the above gain, polarity, and reference source and selects Channels AIN3–AIN4.
9、Write 0x58 to the communications register: This specifies that the next operation is a write of the data register.
10、Poll DOUT/RDY: Poll the DOUT/RDY pin to determine if valid data is available in the data register. When DOUT/RDY goes low, apply 24 serial clocks to clock the data from the ADC. A read should not be initiated when DOUT/RDY is high
11、Continually running through this loop will allow data to be read from each of the channels continuously.
2、What is the sequence of events when converting on several channels for the AD719x when the sequencer is enabled and continuous conversion mode is selected?
When the sequencer is enabled, the ADC automatically sequences through the enabled channels. When several channels are enabled, the bit DAT_STA in the mode register should be set to 1. When DAT_STA equals 1, the contents of the status register are output with each conversion. The LSBs of the status register indicate the channel to which the conversion corresponds.
The sequence of events using the AD7190/AD7192, for example, is as follows (Channels AIN1–AIN2 and AIN3–AIN4 being used). The operating conditions for both channels are 50 Hz output data rate, internal master clock, gain = 1, buffer on, bipolar mode; external reference applied between REFIN1(+) and REFIN1(–) is reference source for the ADC.
1、Write 0x8 to communications register: This specifies that the next operation is a write to the mode register.
2、Write 0x180060 to mode register: This configures the AD719x for an output data rate of 50 Hz; the internal clock is used and DAT_STA is set to 1.
3、Write 0x10 to communications register: This specifies that the next operation is a write to the configuration register.
4、Write 0x000310 to configuration register: This configures the AD719x for the above gain, polarity, and reference source and selects Channels AIN1–AIN2 and AIN3–AIN4.
5、Continuously running the following loop allows conversions to be read back from the two channels continuously.
6、Write 0x58 to the communications register: This specifies that the next operation is a write of the data register.
7、Poll DOUT/RDY: Poll the DOUT/RDY pin to determine if valid data is available in the data register. When DOUT/RDY goes low, apply 32 serial clocks to clock the data from the ADC. A read should not be initiated when DOUT/RDY is high
3、What is the sequence of events when switching between channels for the AD719x when the sequencer is enabled and continuous read mode is selected?
When the sequencer is enabled, the ADC automatically sequences through the enabled channels. When several channels are enabled, the bit
DAT_STA in the mode register should be set to 1. When DAT_STA equals 1, the contents of the status register are output with each conversion. The LSBs of the status register indicate the channel to which the conversion corresponds. With continuous read mode enabled, the user only needs to apply the SCLK pulses when a conversion is available (RDY goes low)— a write to the communications register for each read of the data register is not required.
The sequence of events using the AD7190/AD7192, for example, is as follows (Channels AIN1–AIN2 and AIN3–AIN4 being used). The operating conditions for both channels are 50 Hz output data rate, internal master clock, gain = 1, buffer on, bipolar mode; external reference applied between REFIN1(+) and REFIN1(–) is reference source for the ADC.
1、Write 0x8 to communications register: This specifies that the next operation is a write to the mode register.
2、Write 0x180060 to mode register: This configures the AD719x for an output data rate of 50 Hz, the internal clock is used and DAT_STA is set to 1.
3、Write 0x10 to communications register: This specifies that the next operation is a write to the configuration register.
4、Write 0x000310 to configuration register: This configures the AD719x for the above gain, polarity, and reference source and selects Channels AIN1–AIN2 and AIN3–AIN4.
5、Write 0x5C to the communications register: This specifies that the serial interface is dedicated to continuously read the data register until this function is disabled.
6、Continuously running the following loop allows conversions to be read back from the two channels continuously.
7、Poll DOUT/RDY: Poll the DOUT/RDY pin to determine if valid data is available in the data register. When DOUT/RDY goes low, apply 32 serial clocks to clock the data from the ADC. A read should not be initiated when DOUT/RDY is high.
8、To disable continuous read mode, the command 0x58 is written to the communications register when is low
4、If a conversion is not read and the next conversion is complete, for how long does DOUT/RDY go high?
The DOUT/RDY pin goes high for approximately 100 µs when the master clock is 4.9 MHz. During this time, the data register is updated with the new conversion data so the user should not attempt to read the data register.
5、When single conversion mode is used, can CS be taken high after the single conversion is initiated?
The serial interface is independent of the sampling process. So, once the single conversion is initiated, the AD719x will power up and perform the single conversion irrespective of the CS polarity. So, the user can take CS low, initiate the single conversion and then take CS high again. When the conversion is complete, CS can be taken low to read the conversion and another single conversion can be started if required.
When CS is taken high, the DOUT/RDY pin is tristated. Therefore, the DOUT/RDY pin will not indicate the end of the conversion. The user can determine the end of the conversion by reading the status register. Alternatively, the conversion time could be timed out by the microcontroller clock.
6、Is the serial interface reset when CS is taken high?
No. CS does not reset the serial interface. To reset the serial interface, 40 1s must be written to the ADC. This will reset the on-chip registers
to their default values also.
This architecture was used as it allows the user to read or write to the AD719x in “batches.” For example, when reading the configuration register,the contents can be read as a continuous 24-bit word or the data can be split into three 8-bit bytes. When writing to the configuration register, the information can be sent as a continuous 24-bit word; alternatively, the data can be sent as three 8-bit bytes. CS can be held low when the information is being transferred. Alternatively, CS can be used to frame each of the 8-bit bytes without affecting the data transfer process.
7、When information (conversion data or information from the on-chip registers) is read from the ADC, the LSB readback is always 1. Why?
The DOUT and RDY functions share a pin on the AD719x. So, the DOUT/RDY pin functions are a ready pin when CS is low. Every time a conversion is completed, the pin goes low, indicating to the microprocessor that a valid conversion is available. When the user requests a read of the data register, the DOUT/RDY pin functions are a DOUT pin. When pulses are applied to the SCLK pin, the data is placed on the DOUT pin. The data is output from the AD719x following the SCLK falling edge and is valid on the SCLK rising edge.
When the LSB of the data is placed on the DOUT/RDY pin, the DOUT/RDY pin changes its functionality so that it operates as a RDY pin. The change from the DOUT to RDY the function occurs a few nanoseconds after the SCLK rising edge. The microprocessor is latching the bits on the SCLK rising edge. So, if the microprocessor is slow, then the DOUT/RDY pin is functioning as a RDY pin when the LSB is latched into the microprocessor. So, the microprocessor reads the value of the RDY pin rather than the LSB, causing the LSB to be a 1. To prevent this, a faster microprocessor must be used.
Alternatively, general-purpose input/output pins of the microprocessor can be used to represent a serial interface. By bit-banging, the user has more control over the read instant. By reading the values on the DOUT pin when SCLK is low rather than latching in the data on the SCLK rising edge, all bits of the data read will be valid。