ARM GIC-400 寄存器

1.簡介

GIC-400是用於控制中斷的。在cubieboard2 上 的A20芯片采用了這款控制器。

cubieboard2 的GIC控制器 的地址是0x01C80000---0x01C87FFF ，長度等於GIC-400寄存器的長度。

具體的內容如下所示。

以0x01C80000為起始地址，下面給出的是偏移：

0x0000-0x0FFF	Reserved 未使用，無用
0x1000-0x1FFF	Distributor 配置器 有用
0x2000-0x3FFF	CPU interfaces CPU接口 有用
0x4000-0x4FFF	Virtual interface control block, for the processor that is performing the access 虛擬化相關，無用
0x5000-0x5FFF	Virtual interface control block, for the processor selected by address bits [11:9] 虛擬化相關，無用
	0x5000-0x51FF 0x5200-0x53FF ... 0x5E00-0x5FFF	Alias for Processor 0  Alias for Processor 1 ... Alias for Processor 7
0x6000-0x7FFF	Virtual CPU interfaces 虛擬化相關，無用

常用的是圖中第二塊和第三塊，0x1000~0x3fff這部分的配置。

2.Distributor 配置器

distributor這塊寄存器的地址 = GIC控制器 的地址 + 0x1000 ，使用的時候別忘記了偏移。然后從這里開始，有如下的寄存器

偏移	名稱	可讀寫	復位后	作用
0x000	GICD_CTLR	RW	0x00000000[c]	Distributor Control Register 寫入1使能控制器，必備
0x004	GICD_TYPER	RO	Configuration-dependent[d]	Interrupt Controller Type Register 其中可以查看中斷線的總數
0x008	GICD_IIDR	RO	0x0200143B	Distributor Implementer Identification Register, GICD_IIDR 存了一些版本信息，沒用
0x080-0x0BC	GICD_IGROUPRn	RW	0x00000000	Interrupt Group Registers[e] 一個位圖，控制中斷屬於A組還是B組
0x100	GICD_ISENABLERn	RW[f]	SGIs and PPIs:0x0000FFFF[g]	Interrupt Set-Enable Registers 一個位圖，用於使能各個中斷，寫入1使能。有用
0x104-0x13C			SPIs: 0x00000000
0x180	GICD_ICENABLERn	RW[f]	0x0000FFFF[g]	Interrupt Clear-Enable Registers 和上一個寄存器類似，作用相反，寫入1禁止。
0x184-0x1BC			0x00000000
0x200-0x23C	GICD_ISPENDRn	RW	0x00000000	Interrupt Set-Pending Registers pend位圖，寫入1可以進入pend狀態
0x280-0x2BC	GICD_ICPENDRn	RW	0x00000000	Interrupt Clear-Pending Registers 同上，寫入1效果相反，阻止pend狀態
0x300-0x33C	GICD_ISACTIVERn	RW	0x00000000	Interrupt Set-Active Registers 位圖，寫入1可以激活中斷
0x380-0x3BC	GICD_ICACTIVERn	RW	0x00000000	Interrupt Clear-Active Registers 寫入1反激活中斷
0x400-0x5FC	GICD_IPRIORITYRn	RW	0x00000000	Interrupt Priority Registers 存着各個中斷的優先級，每8位算一個
0x800-0x81C	GICD_ITARGETSRn	RO[h]	-	Interrupt Processor Targets Registers[i] 某個中斷應該發往哪個處理器進行處理
0x820-0x9FC		RW	0x00000000
0xC00	GICD_ICFGRn	RO	SGIs: 0xAAAAAAAA	Interrupt Configuration Registers, GICD_ICFGRn 配置中斷是低電平觸發還是下降沿觸發
0xC04		RO	PPIs: 0x55540000
0xC08-0xC7C		RW[j]	SPIs: 0x55555555
0xD00	GICD_PPISR	RO	0x00000000	Private Peripheral Interrupt Status Register, GICD_PPISR 一般沒用
0xD04-0xD3C	GICD_SPISRn	RO	0x00000000	Shared Peripheral Interrupt Status Registers, GICD_SPISRn 沒用
0xF00	GICD_SGIR	WO	-	Software Generated Interrupt Register 控制軟中斷
0xF10-0xF1C	GICD_CPENDSGIRn	RW	0x00000000	SGI Clear-Pending Registers 軟中斷的pend位
0xF20-0xF2C	GICD_SPENDSGIRn	RW	0x00000000	SGI Set-Pending Registers 同上，不過寫入1時停止pend
0xFD0	GICD_PIDR4	RO	0x00000004	Peripheral ID 4 Register
0xFD4	GICD_PIDR5	RO	0x00000000	Peripheral ID 5 Register
0xFD8	GICD_PIDR6	RO	0x00000000	Peripheral ID 6 Register
0xFDC	GICD_PIDR7	RO	0x00000000	Peripheral ID 7 Register
0xFE0	GICD_PIDR0	RO	0x00000090	Peripheral ID 0 Register
0xFE4	GICD_PIDR1	RO	0x000000B4	Peripheral ID 1 Register
0xFE8	GICD_PIDR2	RO	0x0000002B	Peripheral ID 2 Register
0xFEC	GICD_PIDR3	RO	0x00000000	Peripheral ID 3 Register
0xFF0	GICD_CIDR0	RO	0x0000000D	Component ID 0 Register
0xFF4	GICD_CIDR1	RO	0x000000F0	Component ID 1 Register
0xFF8	GICD_CIDR2	RO	0x00000005	Component ID 2 Register
0xFFC	GICD_CIDR3	RO	0x000000B1	Component ID 3 Register

 

3.cpu接口

開始地址的偏移量為0x2000

Offset	Name	Type	Reset	Description[a]
0x0000	GICC_CTLR	RW	0x00000000	CPU Interface Control Register  使能位。寫入1使能
0x0004	GICC_PMR	RW	0x00000000	Interrupt Priority Mask Register 限制中斷最低優先級，高於此值無法中斷，最好寫大一點
0x0008	GICC_BPR	RW	0x00000002[b]	Binary Point Register The minimum value of the Binary Point Register depends on which security-banked copy is considered: 0x2 Secure copy 0x3 Non-secure copy 優先級分組
0x000C	GICC_IAR	RO	0x000003FF	Interrupt Acknowledge Register 只讀，中斷id
0x0010	GICC_EOIR	WO	-	End of Interrupt Register 寫入以告知cpu已經處理完中斷
0x0014	GICC_RPR	RO	0x000000FF	Running Priority Register 當前中斷優先級
0x0018	GICC_HPPIR	RO	0x000003FF	Highest Priority Pending Interrupt Register [c] 最高優先級中斷號及其pend值
0x001C	GICC_ABPR	RW	0x00000003	Aliased Binary Point Register[d] The minimum value of the Aliased Binary Point Register is 0x3. 別名寄存器
0x0020	GICC_AIAR	RO	0x000003FF	Aliased Interrupt Acknowledge Register[d] 別名寄存器
0x0024	GICC_AEOIR	WO	-	Aliased End of Interrupt Register[d] 別名寄存器
0x0028	GICC_AHPPIR	RO	0x000003FF	Aliased Highest Priority Pending Interrupt Register[c][d] 別名寄存器
0x00D0	GICC_APR0	RW	0x00000000	Active Priority Register 用於保存和恢復
0x00E0	GICC_NSAPR0	RW	0x00000000	Non-Secure Active Priority Register[d] 用於保存和恢復
0x00FC	GICC_IIDR	RO	0x0202143B	CPU Interface Identification Register, GICC_IIDR 存着版本信息
0x1000	GICC_DIR	WO	-	Deactivate Interrupt Register