quartus II 自動生成testbench

如果自己不想寫這些testbench 的這些固定格式，可以在quartus 里自動生成testbench 文件的模板，然后往里面寫信號就行了

步驟：processing->start->starttest bench template write

這里需要注意的是要在仿真選項里選擇一個仿真工具，然后才會生成testbench

自動生成的testbench 模板格式如下：

以一位全加器f_adder的testbench為例

-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to   
-- suit user's needs .Comments are provided in each section to help the user  
-- fill out necessary details.                                                
-- ***************************************************************************
-- Generated on "12/01/2015 20:34:30"
                                                            
-- Vhdl Test Bench template for design  :  f_adder
-- 
-- Simulation tool : ModelSim-Altera (VHDL)
-- 

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY f_adder_vhd_tst IS
END f_adder_vhd_tst;
ARCHITECTURE f_adder_arch OF f_adder_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL ain : STD_LOGIC;
SIGNAL bin : STD_LOGIC;
SIGNAL cin : STD_LOGIC;
SIGNAL cout : STD_LOGIC;
SIGNAL sum : STD_LOGIC;  --所要信號的聲明

COMPONENT f_adder
    PORT (
    ain : IN STD_LOGIC;
    bin : IN STD_LOGIC;
    cin : IN STD_LOGIC;
    cout : OUT STD_LOGIC;
    sum : OUT STD_LOGIC
    );
END COMPONENT;
BEGIN
    i1 : f_adder
    PORT MAP (
-- list connections between master ports and signals
    ain => ain,
    bin => bin,
    cin => cin,
    cout => cout,
    sum => sum
    );
init : PROCESS                                               
-- variable declarations                                     
BEGIN                                                        
        -- code that executes only once                      
WAIT;                                                       
END PROCESS init;                                           
always : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
        -- code executes for every event on sensitivity list  
WAIT;                                                        
END PROCESS always;                                          
END f_adder_arch;

這個時候若是直接把該文件進行仿真是不行的，因為里面的激勵信號沒有初始化（仿真出來的波形會是紅色的不確定值）

 

可以根據需要把信號初始化，例如下面這種：

SIGNAL ain : STD_LOGIC :='1';
SIGNAL bin : STD_LOGIC :='0';
SIGNAL cin : STD_LOGIC :='1';
SIGNAL cout : STD_LOGIC;
SIGNAL sum : STD_LOGIC;