APB(Advanced Peripheral Bus)，外圍總線的意思。該總線協議是ARM公司提出的AMBA總線結構之一，幾乎已成為一種標准的片上總線結構。APB可以向上連接至AHB-Lite和AXI總線。APB的每個傳輸都在時鍾上升沿處罰，每個傳輸至少消耗兩個時鍾周期。Amba 3新加入了PREADY和PSLVERR。
1、Amba 3 APB的信號列表如下表：
| Signal |
Source |
Description |
| PCLK |
Clock source | APB Clk |
| PRESETn |
System bus equivalent | Reset. The APB reset signal is active LOW. This signal is normally connected directly to the system bus reset signal. |
| PADDR | APB bridge | Address. This is the APB address bus. It can be up to 32 bits wide and is driven by the peripheral bus bridge unit. |
| PSELx | APB bridge | Select. The APB bridge unit generates this signal to each peripheral bus slave.It indicates that the slave device is selected and that a data transfer is required.There is a PSELx signal for each slave. |
| PENABLE | APB bridge | Enable. This signal indicates the second and subsequent cycles of an APB transfer. |
| PWRITE | APB bridge | Direction. This signal indicates an APB write access when HIGH and an APB read access when LOW. |
| PWDATA | APB bridge | Write data. This bus is driven by the peripheral bus bridge unit during write cycles when PWRITE is HIGH. This bus can be up to 32 bits wide. |
| PREADY | Slave interface | Ready. The slave uses this signal to extend an APB transfer. |
| PRDATA | Slave interface | Read Data. The selected slave drives this bus during read cycles when PWRITE is LOW. This bus can be up to 32-bits wide. |
| PSLVERR | Slave interface | This signal indicates a transfer failure. APB peripherals are not required to support the PSLVERR pin. This is true for both existing and new APB peripheral designs. Where a peripheral does not include this pin then the appropriate input to the APB bridge is tied LOW. |
2、 APB總線的狀態轉移圖
IDLE：狀態機默認狀態；
SETUP：有傳輸發生后就轉到此狀態，對應的PSELx被選中，該狀態通常持續一個時鍾周期，在下個上升沿進入ACCESS；
ACCESS：PENABLE信號使能，從SETUP到ACCESS，PADDR、PSELx、PWRITE、PWDATA的值須保持穩定不變。來自Slave的PREADY信號控制從ACCESS狀態向下轉變，PREADY=0，繼續保持在ACCESS狀態，延長ACCESS以等待Slave；PREADY=1，若沒有其他傳輸，直接進入IDLE，若有后續傳輸，則直接進入SETUP狀態。