FPGA 移交代碼學習——Map錯誤 ODDR2 使用問題

這段時間一直忙貼片生產相關事情，又是搬家，都沒有什么時間好好整整。

前人移交過來的記錄儀代碼，發現一個BUG ，

 

wire [8:0] fchk_shift_r1 = fenergy_chk<<1;
wire [9:0] fchk_shift_r2 = fenergy_chk<<2;
wire [10:0]fchk_shift_r3 = fenergy_chk<<3;
wire [11:0]fchk_shift_r4 = fenergy_chk<<4;

wire [8:0] fchk_shift_l1 = fenergy_chk>>1;
wire [9:0] fchk_shift_l2 = fenergy_chk>>2;
wire [10:0]fchk_shift_l3 = fenergy_chk>>3;
wire [11:0]fchk_shift_l4 = fenergy_chk>>4;

上面的命名和操作反了，正是如此導致我們該模塊一直工作不正常

然而僅僅將>>改成了<< ，綜合能過，MAP出現如下錯誤：

ERROR:Place:1205 - This design contains a global buffer instance,
<UUT_DCM/clkout1_buf>, driving the net, <clk12M_OBUF>, that is driving the
following (first 30) non-clock load pins off chip.
< PIN: clk12M.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due
to limitations in the global routing. If the design does route there may be
excessive delay or skew on this net. It is recommended to use a Clock
Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
.C1. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue. Although the net
may still not route, you will be able to analyze the failure in FPGA_Editor.
< PIN "UUT_DCM/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >

 

參考：

Xilinx spartan6 ODDR2的用法！ - chen.terry - 中國電子頂級開發網(EETOP)-電子設計論壇、博客、超人氣的電子工程師資料分享平台 - Powered by X-Space
http://www.eetop.cn/blog/html/04/869304-26543.html

FPGA產生時鍾后輸出時鍾是出現的went_D大調的感覺_百度空間
http://hi.baidu.com/lu_shan_2012/item/13f3b21749fb97422a3e2200

應用ISE自帶的原語，添加ODDR2：

    // ODDR2: Output Double Data Rate Output Register with Set, Reset
    // and Clock Enable.
    // Spartan-6
    // Xilinx HDL Libraries Guide, version 12.3
    ODDR2  #(
    .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
    .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
    .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
    ) 
    U_ODDR2_clk12m (
    .Q(clk12m), // 1-bit DDR output data
    .C0(oddr2_12m), // 1-bit clock input
    .C1(~oddr2_12m), // 1-bit clock input
    .CE(1'b1), // 1-bit clock enable input
    .D0(1'b1), // 1-bit data input (associated with C0)
    .D1(1'b0), // 1-bit data input (associated with C1)
    .R(1'b0), // 1-bit reset input
    .S(1'b0) // 1-bit set input
    );
    // End of ODDR2_inst instantiation

再編譯，又出現如下錯誤：

ERROR:Pack:2531 - The dual data rate register "U_ODDR2_clk12m" failed to join
the "OLOGIC2" component as required. The output signal for register symbol
U_ODDR2_clk12m requires general routing to fabric, but the register can only
be routed to ILOGIC, IODELAY, and IOB.

參考：

Pack:2531 - The dual data rate register "clock_clk... - Xilinx User Community Forums
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Pack-2531-The-dual-data-rate-register-quot-clock-clk-5p3M-quot/td-p/344879

出現此問題是由於 又將ODDR2的輸出結果用在了內部邏輯上

經過查實，其實該輸出管腳已經不需要用了，將其注釋掉之后再編譯：

又出現如下錯誤：

ERROR:ChipScope: One or more invalid signal connections detected.
ERROR:ChipScope: Double-click the AGC_test.cdc icon in the sources window to edit and fix the CDC project.

打開AGC_test.cdc文件

原本可用的文件，在經過更改>><<之后確不行了，

雖然移除該cdc文件，編譯通過~ 但是 所有需要的IO口都沒啦!!!

真的是亂啊! 糾結！待繼續！

另外求教大神，為什么程序這么不穩定的原因，完全是牽一發而動全身~

有什么好的方法對該代碼進行改造入手不~

萬分感謝~