https://www.cnblogs.com/yeungchie/
通過 si 導出電路網表，實際上在 Virtuoso 中通過菜單 File - Export - CDL 和 Calibre LVS 中 Export from schematic viewer 也是通過 si 來導出電路網表的，下面講下如何使用。
如何運行 si
下面是 si 的運行命令， $cdslibFile 為 cds.lib 文件。
si -batch -command netlist -cdslib $cdslibFile
si.env 文件
在 si 的運行路徑下需要提前准備好一個 si.env 文件，si 通過讀取這個文件的內容來配置導出 cdl 所需要的信息。
文件的如何編寫可以參考 help 文檔：
- Virtuoso Shared Tools
- Design Data Translators Reference
- Design Translation Using CDL Out
- Using CDL Out
- Preparing the si.env File
- Using CDL Out
- Design Translation Using CDL Out
- Design Data Translators Reference
簡單看看就行，我一般是直接通過 GUI 界面嘗試導出一份 cdl，然后在運行路徑下會有一份 si.env 文件，下面是一個例子：
simLibName = "stdcel"
simCellName = "TOP"
simViewName = "schematic"
simSimulator = "auCdl"
simNotIncremental = 't
simReNetlistAll = nil
simViewList = '("auCdl" "cdl" "schematic" "cmos_sch" "gate_sch" "cmos.sch" "gate.sch" "symbol")
simStopList = '("auCdl" "cdl")
hnlNetlistFileName = "TOP.cdl"
resistorModel = ""
shortRES = 2000.0
preserveRES = 't
checkRESVAL = 't
checkRESSIZE = 'nil
preserveCAP = 't
checkCAPVAL = 't
checkCAPAREA = 'nil
preserveDIO = 't
checkDIOAREA = 't
checkDIOPERI = 't
checkCAPPERI = 'nil
simPrintInhConnAttributes = 'nil
checkScale = "meter"
checkLDD = 'nil
pinMAP = 'nil
preserveBangInNetlist = 'nil
shrinkFACTOR = 0.0
globalPowerSig = ""
globalGndSig = ""
displayPININFO = 't
preserveALL = 't
setEQUIV = ""
incFILE = "./Subcircuit/3t_device.cdl"
auCdlDefNetlistProc = "ansCdlHnlPrintInst"
這個例子中導出的頂層電路單元是 stdcel/TOP/schematic，我們只關心其中幾個常用的變量：
- simLibName ( Library Name )
stdcel - simCellName ( Top Cell Name )
TOP - simViewName ( View Name )
schematic - hnlNetlistFileName ( Output CDL Netlist File )
- incFILE ( Include File )
- auCdlDefNetlistProc ( Analog Netlisting Type )
這個變量決定 pin 的連接方式- ansCdlSubcktCall ( Connection By Order )
順序連接 - ansCdlHnlPrintInst ( Connection By Name )
命名端口連接，一般選擇這個來保證 IP/Digital 網表的連接
- ansCdlSubcktCall ( Connection By Order )
Output/Run Directory 可以直接由輸出網表的路徑來決定。
編寫腳本 export_cdl
明白了 si 的使用方法，現在可以寫一個 shell 腳本，在 Terminal 操作，實現便捷地導出指定電路單元的 cdl 文件。
點擊查看完整代碼
#!/bin/bash
#--------------------------
# Program : export_cdl.sh
# Language : Bash
# Author : YEUNGCHIE
# Version : 2022.04.03
#--------------------------
HelpDoc(){
cat <<EOF
-------------------------------------------------
Export CDL ( Circuit Description Language ) File
-------------------------------------------------
Usage: export_cdl -cdslib cdslibFile -lib libName -cell cellName [ OPTIONS ]
-cdslib Path of cds.lib file
-lib Schematic top cell libName
-cell Schematic top cell cellName
-view Schematic top cell viewName ( Default: schematic )
-file Output netlist file name ( Default: ./<cellName>.cdl )
-include Include subckt file name
-order Netlisting Type Connection By Order ( The default is By Name )
-h, -help Display this help
Examples: export_cdl -cdslib ./cds.lib -lib Xeon -cell X999 -include ./subckt.cdl
Output: Netlist file: X999.cdl
EOF
}
for a in $@; do
if [[ $a =~ ^-+h(elp)? ]]; then
HelpDoc >&2
exit 1
fi
done
unset libName
unset cellName
unset viewName
unset netlistFile
unset cdslibFile
unset includeFile
unset includeFiles
unset connType
viewName='schematic'
connType='ansCdlHnlPrintInst'
# 命令行參數分析
while [[ -n $1 ]]; do
case $1 in
-lib) shift; libName=$1 ;;
-cell) shift; cellName=$1 ;;
-view) shift; viewName=$1 ;;
-file) shift; netlistFile=$1 ;;
-cdslib) shift; cdslibFile=$1 ;;
-include) shift; includeFile="$includeFile $1" ;;
-order) connType='ansCdlSubcktCall' ;;
*)
echo "Invalid option - '$1'" >&2
echo "Try -h or -help for more infomation." >&2
exit 1
;;
esac
shift
done
# 參數檢查
if [[ ! ( -n $cdslibFile && -n $libName && -n $cellName ) ]]; then
## 缺少必要參數時，打印 help 並退出
HelpInfo >&2
exit 1
elif [[ -f $cdslibFile ]]; then
## 將相對路徑改為絕對路徑
cdslibDir=$(cd $(dirname $cdslibFile); pwd -P)
fileName=$(basename $cdslibFile)
cdslibFile="$cdslibDir/$fileName"
else
## 找不到 cds.lib 文件，打印報錯
echo "No such file - $cdslibFile" >&2
echo "Try -h or -help for more infomation." >&2
exit 1
fi
for f in $includeFile; do
f=$(cd $(dirname $f); pwd -P)/$(basename $f)
includeFiles="$includeFiles $f"
done
## 當網表文件名未定義時，設置默認文件名
if [[ -z $netlistFile ]]; then netlistFile="${cellName}.cdl" ; fi
runDir=$(dirname $netlistFile)
netlistFile=$(basename $netlistFile)
if [[ ! -w $runDir ]]; then
echo "Cannot access run directory - $runDir" >&2
exit 1
fi
# si.env 文件生成
cat > $runDir/si.env <<EOF
simLibName = "$libName"
simCellName = "$cellName"
simViewName = "$viewName"
simSimulator = "auCdl"
simNotIncremental = 't
simReNetlistAll = nil
simViewList = '("auCdl" "cdl" "schematic" "cmos_sch" "gate_sch" "cmos.sch" "gate.sch" "symbol")
simStopList = '("auCdl" "cdl")
simNetlistHier = t
hnlNetlistFileName = "$netlistFile"
resistorModel = ""
shortRES = 2000.0
preserveRES = 't
checkRESVAL = 't
checkRESSIZE = 'nil
preserveCAP = 't
checkCAPVAL = 't
checkCAPAREA = 'nil
preserveDIO = 't
checkDIOAREA = 't
checkDIOPERI = 't
checkCAPPERI = 'nil
simPrintInhConnAttributes = 'nil
checkScale = "meter"
checkLDD = 'nil
pinMAP = 'nil
preserveBangInNetlist = 'nil
shrinkFACTOR = 0.0
globalPowerSig = ""
globalGndSig = ""
displayPININFO = 't
preserveALL = 't
setEQUIV = ""
incFILE = "$includeFiles"
auCdlDefNetlistProc = "$connType"
EOF
# 運行 si
si $runDir -batch -command netlist -cdslib $cdslibFile
status=$?
# 刪除中間文件
if [[ -f .stimulusFile.auCdl ]]; then rm -rf .stimulusFile.auCdl ; fi
if [[ -f si.env ]]; then rm -rf si.env ; fi
if [[ -f netlist ]]; then rm -rf netlist ; fi
if [[ -d ihnl ]]; then rm -rf ihnl ; fi
if [[ -d map ]]; then rm -rf map ; fi
exit $status
運行實例
例：cdslib 文件為 ./cds.lib
-
導出
verify庫中的ad01d0單元的電路網表。export_cdl -cdslib cds.lib -lib verify -cell ad01d0導出的 cdl 文件名為
ad01d0.cdl -
導出
verify庫中的inv0d0單元的電路網表，同時包含 subckt 網表文件./netlist，並指定 cdl 文件名為inv.cdl。export_cdl -cdslib ./cds.lib -lib verify -cell inv0d0 -include ./netlist導出的 cdl 文件名為
inv.cdl