1 PCI IP設計
雖然PCI已經逐漸淘汰，但是還是有不少應用需要這樣的接口通訊。
設計目的是為了提供基於源碼的PCI IP，這樣硬件就不必受限於某一個FPGA型號，也方便ASIC遷移。由於PCI的電氣標准都是標准3.3V電平，不像PCIe需要高速收發器、8b/10b編碼等技術的支持，因此設計一個基於源碼的PCI IP是完全可行的，並且我們設計的IP也確實經過了驗證。
1.1 功能需求
l 接收FPGA其它模塊的參數設置，由外部參數決定何時啟動、停止PCI數據傳輸
l 兼容PCI 2.2 協議，33Mhz主頻，32bit地址/數據
l 工作在Target模式，可接收數據讀寫、寄存器讀寫
l 總線狀態監測，具備錯誤匯報能力，並根據錯誤類型決定后續動作，比如重試、停止當前傳輸
1.2 IP特性
l 標准32位33Mhz PCI Target接口;
l Wishbone master接口，支持block/burst讀寫；
l 數據均使用小端模式，可以方便在windows上進行存儲，符合常用習慣；
l 具備標准PCI配置寄存器空間，參數支持修改；
l BAR0 register, 在PCI memory map空間占據32Mbytes；
l 需要支持的PCI指令如下：
0110 Memory Read
0111 Memory Write
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1110 Memory Read Line
1111 Memory Write and Invalidate
l 支持對PCI讀寫進行重試，用戶可通過wishbone master接口發起；
1.3 接口定義/引腳描述
圖 5‑1 PCI Core接口與參數列表(在VIVADO中的形式)
接口主要分成2個部分：
l PCI target接口；
l Wishbone master接口；
參數說明：
l Bars “1BARMEM"/"1BARIO"，支持memory 模式和IO模式，推薦使用默認memory模式；
l Wb endian: wishbone總線使用大端還是小端模式，推薦使用默認小端模式；
l Wb size: wishbone bus size，推薦使用默認32 ；
l Class code ID: PCI class code id;
l Device ID: PCI device id，可以自由指定，當前設備的ID；
l Revision ID: PCI Revision ID，可以自由指定，當前固件的版本；
l Subsystem ID: 子系統ID，一般和Device ID相同，也可以不同；
l Subsystem Vendor ID: 子系統廠商ID，由用戶指定，一般會和Vendor ID相同；
l Vendor ID: PCI提供商ID，表面設備生產廠商，正式的Vendor ID需要向PCI SIG申請，但是在特定系統使用時，可以由用戶自己指定，只要不和現有設備沖突即可；
因為CPU依靠Vendor ID和Device ID來區分不同類型的設備。
接口類型聲明
引腳輸入輸出方向：
In standard input only
out standard output only
t/s Tri-State is a bi-directional, tri-state input/output pin
s/t/s 在時序上要對這類信號多加注意，避免時序出錯。Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agent at a time. The agent that drives an s/t/s pin low must drive it high for at least one clock before letting it float. A
new agent cannot start driving a s/t/s signal any sooner than one clock
after the previous owner tri-states it. A pullup is required to sustain
the inactive state until another agent drives it and must be provided by
the central resource.
o/d Open Drain allows multiple devices to share as a wire-OR. A pull-up is required to sustain the inactive state until another agent drives it and must be provided by the central resource.
1.3.1 內部用戶接口
內部接口即用戶接口，是wishbone master接口，本小節介紹接口定義與關鍵時序。
| 名稱 |
方向 |
分組 |
定義 |
| wb_adr_o |
out |
Internal pins |
Whisbone address |
| wb_dat_i |
in |
Internal pins |
Whisbone data in |
| wb_dat_o |
out |
Internal pins |
Whisbone data out |
| wb_sel_o |
out |
Internal pins |
Whisbone data byte selection . The select output array [SEL_O()] indicates where valid data is expected on the [DAT_I()] signal array during READ cycles, and where it is placed on the [DAT_O()] signal array during WRITE cycles. 表征當前bit對應的byte數據有效，數據周期一般是0xf，表示32bit數據全部有效 |
| wb_we_o |
out |
Internal pins |
Whisbone write enable. The write enable output [WE_O] indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles. 表征當前操作是讀還是寫 |
| wb_stb_o |
out |
Internal pins |
Whisbone data strobe. The strobe output [STB_O] indicates a valid data transfer cycle. It is used to qualify various other signals on the interface such as [SEL_O()]. The SLAVE asserts either the [ACK_I], [ERR_I] or [RTY_I] signals in response to every assertion of the [STB_O] signal 數據有效標志 |
| wb_cyc_o |
out |
Internal pins |
Whisbone cycle. The cycle output [CYC_O], when asserted, indicates that a valid bus cycle is in progress. The signal is asserted for the duration of all bus cycles. For example, during a BLOCK transfer cycle there can be multiple data transfers. The [CYC_O] signal is asserted during the first data transfer, and remains asserted until the last data transfer. 會在整個數據傳輸周期保持有效 |
| wb_ack_i |
in |
Internal pins |
Whisbone acknowledge. The acknowledge input [ACK_I], when asserted, indicates the normal termination of a bus cycle.如果是block傳輸，則可能一直有效 |
| wb_rty_i |
in |
Internal pins |
Whisbone retry. The retry input [RTY_I] indicates that the interface is not ready to accept or send data, and that the cycle should be retried. Slave要求master重試 |
| wb_err_i |
in |
Internal pins |
Whisbone error. The error input [ERR_I] indicates an abnormal cycle termination. |
| wb_int_i |
in |
Internal pins |
Whisbone interrupt. 中斷引腳，實際並不使用 |
1.3.2 Wish bone讀寫時序
圖 5‑2 PCI通過wishbone接口進行單次讀取，這里可以用做讀寫用戶寄存器，wb_stb_o&wb_cyc_o==1時，當前讀請求有效，slave在下一個時鍾周期進行回應，同時返回指定地址的數據
圖 5‑3 PCI通過wishbone接口進行單次寫入，這里可以用做用戶寄存器寫入，wb_stb_o&wb_cyc_o==1時，當前讀請求有效，slave在下一個時鍾周期進行回應，表面請求寫入的動作已經完成。
圖 5‑4 PCI block read方式讀，可以用做DMA數據讀取，PCI的讀操作轉換成wishbone的讀操作，wb_stb_o&wb_cyc_o==1時，當前讀請求有效，在下一個時鍾周期返回有效數據，最后一個周期的讀請求無需響應。
圖 5‑5 PCI block write方式寫入，可以用做DMA數據寫入，PCI的讀操作轉換成wishbone的寫操作，wb_stb_o&wb_cyc_o==1時，當前寫請求有效，在下一個時鍾周期返回寫完成相應，最后一個周期的寫請求無需響應。
1.3.3 PCI物理接口
參考來自PCI SPEC V2.2
表 5‑3 PCI接口
| 名稱 |
方向 |
分組 |
定義 |
| clk33 |
in |
System pins |
Clock provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals, except RST#, INTA#, INTB#, INTC#, and INTD#, are sampled on the rising edge of CLK and all other timing parameters are defined with respect to this edge 該信號應來自板載晶振 |
| rst |
in |
System pins |
Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state. Anytime RST# is asserted, all PCI output signals must be driven to their benign state. In general, this means they must be asynchronously tri-stated. REQ# and GNT# must both be tristated (they cannot be driven low or high during reset). To prevent AD, C/BE#, and PAR signals from floating during reset, the central resource may drive these lines during reset (bus parking) but only to a logic low level; they may not be driven high. 該信號來自板載復位 |
| ad [31:0] |
t/s |
Address and Data Pins |
Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address2 phase followed by one or more data phases. PCI supports both read and write bursts. |
| cbe [3:0]# |
t/s |
Address and Data Pins |
Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3::0]# define the bus command (refer to Section 3.1. for bus command definitions). During the data phase, C/BE[3::0]# are used as Byte Enables |
| par |
t/s |
Address and Data Pins |
Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI agents. Parity generation is not optional, it must be done by all PCI-compliant devices 偶檢驗是必須實現的功能 |
| frame# |
s/t/s |
Interface Control Pins |
Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is deasserted, the transaction is in the final data phase or has completed. 讀寫時序圖上可以看到傳輸是如何結束的 |
| irdy# |
s/t/s |
Interface Control Pins |
Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are asserted. During a write, IRDY# indicates that valid data is present on AD[31::00]. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. |
| trdy# |
s/t/s |
Interface Control Pins |
Target Ready indicates the target agent’s (selected device’s) ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on any clock both TRDY# and IRDY# are asserted. During a read, TRDY# indicates that valid data is present on AD[31::00]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. |
| stop |
s/t/s |
Interface Control Pins |
Stop indicates the current target is requesting the master to stop the current transaction. |
| devsel |
s/t/s |
Interface Control Pins |
Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. |
| idsel |
in |
Interface Control Pins |
Initialization Device Select is used as a chip select during configuration read and write transactions. |
| perr# |
s/t/s |
Error Reporting Pins |
Parity Error is only for the reporting of data parity errors during all PCI transactions except a Special Cycle. The PERR# pin is sustained tri-state and must be driven active by the agent receiving data (when enabled) two clocks following the data when a data parity error is detected. The minimum duration of PERR# is one clock for each data phase that a data parity error is detected. |
| serr# |
o/d |
Error Reporting Pins |
System Error is for reporting address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. |
| intb# |
o/d |
Interrupt Pins |
Interrupt C is used to request an interrupt and only has meaning on a multi-function device 本項目不會使用該引腳 |
下面是客戶提供的名稱，其中REQ和GNT是Master專用，本設計實際並不需要
- STOP
- SERR
- PERR
- RST
- FRAME
- TRDY
- DEVSEL
- PAR
- CLK
- INTC
- REQ[3:0] Bus Masters Only，因此不需要
- GNT[3:0] Bus Masters Only，因此不需要
- CBE[3:0]
- AD[31:0]
1.4 狀態機
本部分參考PCI SPEC V2.2中參考狀態機進行修改設計。
以下是spec對狀態機的描述
“Caution needs to be taken when an agent is both a master and a target. Each must have its own state machine that can operate independently of the other to avoid deadlocks. This means that the target state machine cannot be affected by the master state machine. Although they have similar states, they cannot be built into a single machine.”
圖 5‑6 PCI Core狀態機示意圖，實際會多出2個狀態
實際為了將PCI操作轉化為Wishbone讀寫，狀態S_DATA2和TURN_ARE狀態，這兩個狀態主要目的是滿足信號時序邏輯。
狀態機狀態：PCIIDLE, B_BUSY, S_DATA1, S_DATA2, BACKOFF, TURN_ARL, TURN_ARE。詳細跳轉過程可以參照代碼進行理解，文檔對該部分暫時不做詳細說明。
1.5 PCI關鍵時序
該部分將用時序圖的方式，分別對PCI的各種操作給出PCI Spec要求的時序、以及本項目提供的PCI Core實際仿真時序。其中仿真時序中IRDY信號並未嚴格滿足要求(該信號來源於PCI master，本文檔不需要提供PCI master，只是提供仿真模型)，但是並不影響實際結果。
圖 5‑7 讀配置寄存器
圖 5‑8 讀取device id 0x0001，vendor id 0x4150，各占用16bit，其中vendor id占用低16bit，當前圖示時序的irdy比理論多出一個有效的時鍾周期，這只是仿真邏輯pci master的問題，且並不影響數據傳輸的正確性，因此可以忽略
圖 5‑9 寫入PCI配置寄存器，base address registers, 地址0x10，寫入數據0x3000_0000
圖 5‑10 PCI 配置寄存器列表
圖 5‑11 從用戶地址空間讀取用戶寄存器
圖 5‑12 向用戶地址空間寫入寄存器
圖 5‑13 從用戶地址空間以block的方式讀出數據
圖 5‑14 向用戶地址空間以block的方式寫入數據
在仿真代碼中，加入對寄存器讀寫的測試。
start_read =0;
addr =0;
length=1;
rst=1;
#200;
rst=0;
//vendor id device id
pci_configuration_read(0,data_value);
assert(data_value=='h14150);
//cmd status
pci_configuration_read(4,data_value);
assert(data_value=='h02000002);
pci_configuration_write('h10,'h3000_0000);
pci_configuration_read(0,data_value);
assert(data_value=='h14150);
pci_configuration_read('h10,data_value);
assert(data_value=='h3000_0000);
pci_memory_read('h3000_0000,data_value);
assert(data_value==0);
pci_memory_read('h3000_0004,data_value);// address add 4 every time, must increment WBSIZE/8
assert(data_value==1);
pci_memory_read('h3000_0008,data_value);// address add 4 every time
assert(data_value==2);
pci_memory_write('h3000_0000,100);
pci_memory_read('h3000_0000,data_value);
assert(data_value==100);
pci_memory_write('h3000_0000,0);//重新寫0
pci_memory_read_line('h3000_0000,4,data_value);//read line
pci_memory_write_line('h3000_0000,4,111);//write line
pci_memory_read_line('h3000_0000,4, data_value);//read line
pci_memory_read_line('h3000_0000,5, data_value);//read line
pci_memory_read_line('h3000_0000,6, data_value);//read line
pci_memory_read_line('h3000_0010,10, data_value);//read line
1.6 支持的PCI指令
l 支持的PCI指令
0110 Memory Read
0111 Memory Write
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1110 Memory Read Line
1111 Memory Write and Invalidate
下面是一些spec對相關指令的描述，用戶並不需要特別關注下面的內容，這只是開發人員的記錄。
從上面這段話可以看出，單純的memory read 是一次只能讀取4個字節，效率很低。
而memory read line/ memory read multiple自治領推薦實現cache line size 寄存器。下面這段話可以看出cache line size 寄存器所起的作用和約束。
It is highly recommended that the Cacheline Size register be implemented to ensure
correct use of the read commands. 這個只是針對master設備而言，target設備只負責接收請求。
Bridge會讀取比master更多的數據來實現高性能數據傳輸。
那么bridge是有責任負責存儲預取的隱藏數據責任，最簡單的方式是認為該部分數據無效並拋棄，需要注意，這樣的方式不進行小心的處理可能導致數據的丟失。
從6章節關於cache line size寄存器的描述可以看出，對於target類型的slave設備，除非需要支持cacheline wra addressing模式，否則是可以不實現cache line size的，數據的傳輸大小由master設備決定。
圖 5‑15 block read
數據傳輸的終止，取決於master的frame信號，frame信號為高表示要終止傳輸，下一個數據即最后一個數據。