3-8譯碼器/4-16譯碼器的verilo實現（組合邏輯）

module code3_8(a,b,c,out);
    
    //輸入端口
    input a;
    input b;
    input c;
    
    //輸出端口
    output reg [7:0]out;        //【】定義out信號為8位的位寬，高位在前，低位在后
    
    //所有在always@中要賦值的信號都必須定義為reg型
    always@(a,b,c)begin            //abc為敏感信號
        case({a,b,c})        // {}拼接三個信號為一個新的信號
            3'b000:out = 8'b0000_0001;        //下划線為占位符，無實際意義
            3'b001:out = 8'b0000_0010;
            3'b010:out = 8'b0000_0100;
            3'b011:out = 8'b0000_1000;
            3'b100:out = 8'b0001_0000;
            3'b101:out = 8'b0010_0000;
            3'b110:out = 8'b0100_0000;
            3'b111:out = 8'b1000_0000;
            //default:out = xxxxxxxx;    如果不必枚舉全部情況，則用default表示剩余情況
        endcase
    end  

endmodule

`timescale 1ns/1ns

module code3_8_tb;

    reg a;
    reg b;
    reg c;
    
    wire [7:0] out;
    code3_8 u1(
        .a(a),
        .b(b),
        .c(c),
        .out(out)
    );

    initial begin
        a = 0;b = 0;c = 1;
        #200;
        a = 0;b = 1;c = 0;
        #200;
        a = 0;b = 1;c = 1;
        #200;
        a = 1;b = 0;c = 0;
        #200;
        a = 1;b = 0;c = 1;
        #200;
        a = 1;b = 1;c = 0;
        #200;
        a = 1;b = 1;c = 1;
        #200;
        a = 0;b = 0;c = 0;
        #200;
        
        $stop;    
        
        end
    
endmodule

 4-16譯碼器增加一個輸入端口即可