ARM core registers (ARMv7)
ARM v7-A and ARM v7-R
Reference:
ARM ® Architecture Reference Manual(ARM ® v7-A and ARM ® v7-R edition)
Chapter B1 The System Level Programmers’ Model
B1.3 ARM processor modes and core registers
B1.3.2 ARM core registers
- ARM core registers
______________ _________________________________________________________________________________________
| Application | | User | System | Supervisor | Monitor | Abort | Undefined | IRQ | FIQ |
| level view | | Mode | Mode | Mode | Mode | Mode | Mode | Mode | Mode |
|_R0 |_R0_usr
|_R1 |_R1_usr
|_R2 |_R2_usr
|_R3 |_R3_usr
|_R4 |_R4_usr
|_R5 |_R5_usr
|_R6 |_R6_usr
|_R7 |_R7_usr
|_R8 |_R8_usr |_R8_fiq
|_R9 |_R9_usr |_R9_fiq
|_R10 |_R10_usr |_R10_fiq
|_R11 |_R11_usr |_R11_fiq
|_R12 |_R12_usr |_R12_fiq
|_SP |_SP_usr |_SP_svc |_SP_mon |_SP_abt |_SP_und |_SP_irq |_SP_fiq
|_LR |_LR_usr |_LR_svc |_LR_mon |_LR_abt |_LR_und |_LR_irq |_LR_fiq
|_PC |_PC
|_APSR |_CPSR
|_SPSR_svc |_SPSR_mon |_SPSR_abt |_SPSR_und |_SPSR_irq |_SPSR_fiq
|____________________________________________________________________Exception modes
|______________________________________________________________________________Privileged modes
|________________________________________________________________________________________System level views
Monitor mode, and the associated banked of registers, are implemented only as part of the Security Extensions.
Author: Yangkai Wang
wang_yangkai@163.com
2021/05/17
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