2.6 Advanced Error Reporting Capability (Optional)
The Advanced Error Reporting definitions below are based on the PCI Express 2.1 Base specification. Implementations may choose to base the device on a specification beyond the PCI Express 2.1 Base specification. In all cases, the PCI Express Base specification is the normative reference for the Advanced Error Reporting registers.
2.6高級錯誤報告功能（可選）
下面的高級錯誤報告定義基於PCI Express 2.1基本規范。 實施人員可以選擇將設備基於PCI Express 2.1 Base規范以外的規范。 在所有情況下，PCI Express Base規范都是Advanced Error Reporting寄存器的規范參考。
2.6.2 Offset AERCAP + 4: AERUCES – AER Uncorrectable Error Status Register
This register indicates the error detection status of the individual errors on the controller. These bits are sticky – they are neither initialized nor modified during a hot reset or Function Level Reset (FLR).
2.6.2 AERCAP + 4偏移量：AERUCES – AER無法糾正的錯誤狀態寄存器
該寄存器指示控制器上各個錯誤的錯誤檢測狀態。 這些位具有粘性–在熱復位或功能級別復位（FLR）期間既不會初始化也不會對其進行修改。
2.6.3 Offset AERCAP + 8: AERUCEM – AER Uncorrectable Error Mask Register
This register controls the reporting of the individual errors by the controller. A masked error is not reported in the Header Log register (AERHL), does not updated the First Error Pointer (AERCC.FEP), and is not reported to the host. These bits are sticky – they are neither initialized nor modified during a hot reset or FLR.
2.6.3偏移量AERCAP + 8：AERUCEM – AER不可校正錯誤掩碼寄存器
該寄存器控制控制器報告單個錯誤。 在標頭日志寄存器（AERHL）中未報告掩蔽的錯誤，沒有更新第一個錯誤指針（AERCC.FEP），也沒有報告給主機。 這些位具有粘性–在熱復位或FLR期間既不進行初始化也不進行修改。
2.6.4 Offset AERCAP + Ch: AERUCESEV – AER Uncorrectable Error Severity Register
This register controls whether an individual error is reported as a non-fatal or a fatal error. An error is reported as fatal when the corresponding error bit in the severity register is set (‘1’). If the bit is cleared (‘0’), the corresponding error is considered non-fatal. These bits are sticky – they are neither initialized nor modified during a hot reset or FLR.
2.6.4偏移量AERCAP +通道：AERUCESEV – AER不可糾正錯誤嚴重性寄存器
該寄存器控制將單個錯誤報告為非致命錯誤還是致命錯誤。 當嚴重性寄存器中的相應錯誤位被設置為“ 1”時，錯誤被報告為致命錯誤。 如果該位被清除（0），則相應的錯誤被認為是非致命的。 這些位具有粘性–在熱復位或FLR期間既不進行初始化也不進行修改。
2.6.5 Offset AERCAP + 10h: AERCS – AER Correctable Error Status Register
This register reports error status of individual correctable error sources from the controller. These bits are sticky – they are neither initialized nor modified during a hot reset or FLR.
2.6.5偏移量AERCAP + 10h：AERCS – AER可校正錯誤狀態寄存器
該寄存器報告控制器中各個可糾正錯誤源的錯誤狀態。 這些位具有粘性–在熱復位或FLR期間既不進行初始化也不進行修改。
2.6.6 Offset AERCAP + 14h: AERCEM – AER Correctable Error Mask Register
This register controls the reporting of the individual correctable errors by the controller. A masked error is not reported to the host. These bits are sticky – they are neither initialized nor modified during a hot reset or FLR.
2.6.6偏移AERCAP + 14h：AERCEM – AER可校正錯誤掩碼寄存器
該寄存器控制控制器對單個可糾正錯誤的報告。 屏蔽的錯誤不會報告給主機。 這些位具有粘性–在熱復位或FLR期間既不進行初始化也不進行修改。
2.6.8 Offset AERCAP + 1Ch: AERHL – AER Header Log Register
This register contains the header for the TLP corresponding to a detected error. This register is sticky – it is neither initialized nor modified during a hot reset or FLR.
2.6.8偏移AERCAP + 1Ch：AERHL – AER標頭日志寄存器
該寄存器包含與檢測到的錯誤相對應的TLP的標頭。 該寄存器是粘性的–在熱復位或FLR期間既不初始化也不修改。
2.6.9 Offset AERCAP + 38h: AERTLP – AER TLP Prefix Log Register (Optional)
This register contains the End-End TLP prefix(es) for the TLP corresponding to a detected error. This register is sticky – it is neither initialized nor modified during a hot reset or FLR.
2.6.9偏移AERCAP + 38h：AERTLP – AER TLP前綴日志寄存器（可選）
該寄存器包含與檢測到的錯誤相對應的TLP的End-End TLP前綴。 該寄存器是粘性的–在熱復位或FLR期間既不初始化也不修改。
2.7 Other Capability Pointers
Though not mentioned in this specification, other capability pointers may be necessary, depending upon the implementation. Examples would be the PCI-X capability for PCI-X implementations, and potentially the vendor specific capability pointer.
These capabilities are beyond the scope of this specification.
2.7其他能力指標
盡管在本規范中未提及，但根據實現情況，可能還需要其他功能指針。 示例包括用於PCI-X實現的PCI-X功能，以及潛在的供應商特定功能指針。
這些功能超出了本規范的范圍。