1.頂層數碼管顯示模塊
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 18:57:45 08/18/2019 // Design Name: // Module Name: dynamic_seg_top // Project Name: // Target Devices: // Tool versions: // Description: //實現簡易時鍾計數功能 // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // module dynamc_seg_top //---------------------<端口聲明>--------------------------------------- ( input clk_50MHZ , //時鍾，50Mhz input rst_n , //復位，低電平有效 output reg [ 7:0] seg_sel , //數碼管位選 output reg [ 7:0] seg_data //數碼管段選，即內容顯示 ); //---------------------<信號定義>--------------------------------------- wire clk_1KHZ ; reg [3:0] data_tmp ; reg [7:0] cnt ; wire [23:0] data ; //---------------------------------------------------------------------- // 1k分頻例化，掃描一個數碼管時間為1ms //---------------------------------------------------------------------- CLK_DIV # ( .width(16), .cnt(50_000) ) uut( .clk_50MHZ(clk_50MHZ), .rst_n(rst_n), .clk_out(clk_1KHZ) ); //====================================================================== // //時，分，秒計數例化 // //====================================================================== clock_cnt clk_cnt_uut( .clk_50MHZ(clk_50MHZ), .rst_n(rst_n), .data(data) ); //---------------------------------------------------------------------- // 數碼管掃描，8位循環掃描，頻率為1k //---------------------------------------------------------------------- always @(posedge clk_1KHZ or negedge rst_n) begin if(!rst_n) seg_sel <= 8'b0111_1111; else if(seg_sel==8'b1111_1110) seg_sel <= 8'b0111_1111; else seg_sel <= ~(~seg_sel>>1); end //---------------------------------------------------------------------- // 位選，不同計數對應不同位選編碼，也對應分割的不同數據 //---------------------------------------------------------------------- always @(*) begin case(seg_sel) 8'b0111_1111: data_tmp = data[ 3: 0] ; // 位1 8'b1011_1111: data_tmp = data[ 7: 4] ; // 位2 8'b1101_1111: data_tmp = 4'ha ; // 位3 8'b1110_1111: data_tmp = data[11:8] ; // 位4 8'b1111_0111: data_tmp = data[15:12] ; // 位5 8'b1111_1011: data_tmp = 4'hb ; // 位6 8'b1111_1101: data_tmp = data[19:16] ; // 位7 8'b1111_1110: data_tmp = data[23:20] ; // 位8 default: data_tmp = 4'b0000 ; endcase end //---------------------------------------------------------------------- // 段選，將不同分割數據進行段選編碼，實驗平台為2個4位一體共陽數碼管 //---------------------------------------------------------------------- always @(*) begin case(data_tmp) 4'h0: seg_data = 9'hc0; 4'h1: seg_data = 9'hf9; 4'h2: seg_data = 9'ha4; 4'h3: seg_data = 9'hb0; 4'h4: seg_data = 9'h99; 4'h5: seg_data = 9'h92; 4'h6: seg_data = 9'h82; 4'h7: seg_data = 9'hf8; 4'h8: seg_data = 9'h80; 4'h9: seg_data = 9'h90; 4'ha: seg_data = 9'hbf;// 4'hb: seg_data = 9'hbf;//第三位和第六位顯示時鍾的分隔線 default:seg_data = 9'hc0; endcase end endmodule
2.時分秒計數模塊
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 19:51:36 02/25/2020 // Design Name: // Module Name: clock_cnt // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module clock_cnt ( input clk_50MHZ, input rst_n, output [23:0]data ); reg [7:0] second ;//時鍾“秒” reg [7:0] minute ;//時鍾“分” reg [7:0] hour ;//時鍾“小時” wire clk_1HZ ; //---------------------------------------------------------------------- //-- 例化計數分頻產生1HZ時鍾 //---------------------------------------------------------------------- CLK_DIV # ( .width(28), .cnt(50_000_000) ) uut( .clk_50MHZ(clk_50MHZ), .rst_n(rst_n), .clk_out(clk_1HZ) ); //---------------------------------------------------------------------- //-- 秒計數，從0-59計數，1秒加一，到59清零 //---------------------------------------------------------------------- always @(posedge clk_1HZ or negedge rst_n) begin if(!rst_n) second<=8'd0; else if (second[3:0]==4'd9) begin second[3:0]<=8'd0; if(second[7:4]==4'd5) second[7:4]<=4'd0; else second[7:4]<=second[7:4]+4'd1; end else second[3:0]<=second[3:0]+4'd1; end //---------------------------------------------------------------------- //-- 分計數，從0-59計數，1分鍾加一，到59清零 //---------------------------------------------------------------------- always @(posedge clk_1HZ or negedge rst_n) begin if(!rst_n) minute<=8'd0; else if ((second[3:0]==4'd9)&(second[7:4]==4'd5)) begin if(minute[3:0]==4'd9) begin minute[3:0] <=4'd0; if(minute[7:4]==4'd5) minute[7:4] <=4'd0; else minute[7:4] <=minute[7:4]+4'd1; end else begin minute[3:0]<=minute[3:0]+4'd1; end end else minute<=minute; end //---------------------------------------------------------------------- //-- 小時計數，從0-23計數，1小時加一，到23清零 //---------------------------------------------------------------------- always @(posedge clk_1HZ or negedge rst_n) begin if(!rst_n) hour<=8'd0; else if ((second[3:0]==4'd9)&(second[7:4]==4'd5)&(minute[3:0]==4'd9)&(minute[7:4]==4'd5)) begin if(hour[7:4]==4'd2) begin if(hour[3:0]==4'd3) begin hour[3:0] <=4'd0; hour[7:4]<=4'd0; end else begin hour[7:4]<=hour[7:4]; hour[3:0] <=hour[3:0]+4'd1; end end else begin if(hour[3:0]==4'd9) begin hour[3:0] <=4'd0; hour[7:4] <=hour[7:4]+4'd1; end else begin hour[3:0] <=hour[3:0]+4'd1; hour[7:4] <=hour[7:4]; end end end else hour<=hour; end assign data[3:0] =second [3:0];//將“秒”的個位數送到數碼管第一位 assign data[7:4] =second [7:4];//將“秒”的十位數送到數碼管第二位 assign data[11:8] =minute [3:0];//將“分“的個位數送到數碼管第四位 assign data[15:12] =minute [7:4];//將”分”的十位數送到數碼管第五位 assign data[19:16] =hour [3:0];//將“時“的個位數送到數碼管第七位 assign data[23:20] =hour [7:4];//將”時”的個位數送到數碼管第八位 endmodule
3.任意時鍾分頻模塊
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 18:54:40 02/25/2020 // Design Name: // Module Name: CLK_DIV // Project Name: // Target Devices: // Tool versions: // Description: //任意時鍾分頻模塊 // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module CLK_DIV # ( parameter width = 28, parameter cnt = 50_000_000 ) ( input clk_50MHZ, input rst_n , output clk_out ); reg [width-1:0] cnt_p; reg cnt_n; reg clk_p; reg clk_n; //上升沿計數器，實現0-49_999_999計數 always@(posedge clk_50MHZ or negedge rst_n) begin if(!rst_n) cnt_p <= 1'b0; else if(cnt_p == (cnt-1)) cnt_p <= 1'b0; else cnt_p <= cnt_p + 1'b1; end //上升沿觸發時鍾分頻，實現1HZ時鍾輸出 always@(posedge clk_50MHZ or negedge rst_n) begin if(!rst_n) clk_p<=1'b0; else if(cnt_p<(cnt>>1)) clk_p<=1'b0; else clk_p<=1'b1; end always@(negedge clk_50MHZ or negedge rst_n) begin if(!rst_n) cnt_n <= 1'b0; else if(cnt_n == (cnt-1)) cnt_n <= 1'b0; else cnt_n <= cnt_n + 1'b1; end always@(negedge clk_50MHZ or negedge rst_n) begin if(!rst_n) clk_n<=1'b0; else if(cnt_n<(cnt>>1)) clk_n<=1'b0; else clk_n<=1'b1; end wire clk1=clk_50MHZ; //當分頻系數為1時，輸出時鍾 wire clk2=clk_p; //當分頻系數為偶數時，輸出等於clk_p wire clk3=clk_p&clk_n;//當分頻系數為奇數時，輸出等於clk_p&clk_n assign clk_out=(cnt==1)?clk1:(cnt[0]? clk2:clk3); endmodule
4.時分秒仿真testbench文件
`timescale 100ps / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 22:18:22 02/25/2020 // Design Name: clock_cnt // Module Name: C:/mydesign/dybamic_seg1/clk_tb.v // Project Name: dybamic_seg // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: clock_cnt // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module clk_tb; // Inputs reg clk_50MHZ; reg rst_n; // Outputs wire [23:0] data; // Instantiate the Unit Under Test (UUT) clock_cnt uut ( .clk_50MHZ(clk_50MHZ), .rst_n(rst_n), .data(data) ); initial begin // Initialize Inputs clk_50MHZ = 0; rst_n = 0; // Wait 100 ns for global reset to finish #10; rst_n = 1; #10; // Add stimulus here end always #1 clk_50MHZ=~clk_50MHZ; endmodule
5.顯示模塊仿真testbench文件
`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 15:11:16 02/26/2020 // Design Name: dynamc_seg_top // Module Name: C:/mydesign/dybamic_seg1/dy_segtb.v // Project Name: dybamic_seg // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: dynamc_seg_top // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module dy_segtb; // Inputs reg clk_50MHZ; reg rst_n; // Outputs wire [7:0] seg_sel; wire [7:0] seg_data; // Instantiate the Unit Under Test (UUT) dynamc_seg_top uut ( .clk_50MHZ(clk_50MHZ), .rst_n(rst_n), .seg_sel(seg_sel), .seg_data(seg_data) ); initial begin // Initialize Inputs clk_50MHZ = 0; rst_n = 0; // Wait 100 ns for global reset to finish #10; rst_n = 1; #10; // Add stimulus here end always #1 clk_50MHZ=~clk_50MHZ; endmodule