最近重新整理了一下AXI協議里對於ordering的描述，總結在下面，這里其實有很多實現相關的方式，協議里只是給了一些指導意見，對於具體的做法就需要實戰中再看具體情況了，比如ID位寬在哪個節點擴展，系統如果有PCIe的ordering，如何高效的保序，減少性能影響；如果涉及到非一致性域到一致性域的轉換，如何在不同協議之間保序，這些都是實際中遇到過的問題，后面有時間再繼續總結。
Definition of the ordering model:
AXI4 protocol supports an ordering model based on the use of the AXI ID transaction identifier
The principles are that for transactions with the same ID:
- Transactions to any single peripheral device, must arrive at the peripheral in the ordering in which they are issued, regardless of the addresses of the transactions.
- 發向單個device的，必須按順序，不管地址
- Memory transactions that use the same, or overlapping, addresses must arrive at the memory in the order in which they are issued.
- 訪存傳輸，如果地址hazard, 必須按順序
Note:
In an AXI system with multiple masters, the AXI IDs used for the ordering model include the infrastructure IDs, that identify each master uniquely. This means the ordering model applies independently to each master in the system.
每個master單獨執行ordering rules.
The AXI ordering model also requires that all transactions with the same ID in the same direction must provide their responses in the order in which they are issued.
同一個ID同方向的傳輸，response也要in order
Because the read and write address channels are independent, if an ordering ordering relationship is required between two transactions with the same ID that are in different directions, then a master must wait to receive a response to the first transactions before issuing the second transaction.
不同方向的順序要等待，顯而易見，不需要多說
而且即使收到了response, 這個response如果是中間節點給的，也無法保證順序。
Master Ordering
A master that issues multiple transactions in the same direction, read or write, with the same ID has the following guarantees about the ordering of these transactions.
- The order of response at the master to all transactions must be the same as the order of issue.
- Master收到的response要保序
- For transactions to Device memory, the order of arrival at the slave must be the same as the order of issue.
- 發送到device的，到達的順序要保持.
- For normal memory, the order of arrival at the slave of transactions to the same or overlapping addresses, must be the same as the order of issue. This applies also, to transactions to cacheable memory. That is , it applies to all valid transactions for which AxCACHE[3:1] is not 0b000.
- 對於normal memory, 如果地址hazard, 則到達slave要保序。
Interconnect ordering:
To meet the requirements of the ordering model, the interconnect must ensure that:
- The order of transactions in the same direction with the same ID to Device memory is preserved.
- 同方向，同ID，發送到Device的傳輸要保序
- The order of transactions in the same direction with the same ID to the same or overlapping addresses is preserved.
- 同方向，同ID，地址hazard，要保序
- The order of write responses with the same ID is preserved.
- 同ID的write response要保序
- The order of read responses with the same ID is preserved.
- 同ID的read response要保序
- Any manipulation of the AXI ID values associated with a transaction must ensure that the ordering requirements of the original ID values are maintained.
- 對ID的操作，要保證原始ID的順序要求可以滿足
- Any component that gives a response to a transaction before the transaction reaches its final destination must ensure that the ordering requirements given in this section are maintained until the transaction reaches its final destination.
- 對於Posted write, 中間節點要負責完整保序
Slave Ordering
To meet the requirements of the ordering model, a slave must ensure that:
- Any write transaction for which it has issued a response must be observed by any subsequent write or read transaction, regardless of the transaction IDs.
- 對於slave發出的write response, 要保證對后面的讀寫可見，無論ID
- Any write transaction to Device memory must be observed by any subsequent write to Device memory with the same ID, even if a response has not yet been issued.
- 即使沒發response，對Device 的同ID寫也要被后面的寫可見
- 還沒給response，怎么保證能被看到？
- Any write transaction to Normal memory must be observed by any subsequent write to the same or an overlapping address with the same ID, even if a response has not yet been given.
- 對同ID地址hazard的normal memory寫，即使沒有給response，也要能被后面的傳輸看到
- Responses to multiple write transactions with different IDs can be issued in any order.
- 不同ID的response可以亂序
- Any read transaction for which it has issued a response must be observed by any subsequent write or read transaction, regardless of the transaction IDs.
- 不論ID，讀要被后面的操作看到.
- Any read transaction to Device memory must be observed by any subsequent read to Device memory with the same ID, even if a response has not yet been issued.
- 同ID對Device'的訪問，必須被后面的操作看到。
- Responses to multiple read transactions with the same ID must be issued in the order in which the transactions arrive.
- 對於同ID的讀，response要按順序發
- Responses to multiple read transactions with different IDs can be issued in any order.
- 不同ID的讀，response可以亂序
- 如果這樣，read->write->read, 對同一地址的操作，兩次讀數據不同，是否需要保序？
- 如果要保證讀到最新的數據，要么等前一筆write結束，要么是同一個ID。
Response before final destination:
Any intermediate component that issues a transaction response before the transaction has reached its final destination , must ensure visibility of the transaction to any transactions from any upstream masters.
- Posted write, 中間節點要負責保證數據consistency.
The requirements are:
- For accesses to all memory types, any subsequent transaction to the same or an overlapping address must observe the transaction for which the intermediate component issues a response.
- Memory訪問，地址和hazard的后一筆，要能看到前一筆的post write response.
- 如何保證？其實就是保序
- For accesses to Device memory, the intermediate component must also maintain the ordering of any subsequent transaction with the same ID and to the same slave, relative to the transaction for which it issued a response.
- Device訪問，中間節點要對同ID和同slave目標的傳輸保序
An intermediate response can only be given to a transaction when the AxCACHE attribute indicates that it is permissible to do so.
要看AxCache
Transaction marked as Normal can be converted to Device without removing any of its original guarantees. To meet this requirement, the behavior for Device memory accesses to the same or overlapping addresses must be the same as for Normal memory accesses, regardless of the ID values.
對地址hazard，device傳輸也不看ID，要保序
Ordered write observation
To improve compatibility with interface protocols that support a different ordering model an Ordered_Write_Observation property is defined that can be True or False for a single interface.
An interface that supports the Ordered_Write_Observation property can support the Producer/Consumer ordering model with improved performance.
這部分沒有實現上的指導作用
Ordered_Write_Observation property