Q：還有一種RC corner 帶后綴『_T』，只用於setup signoff，T指的是什么？
A：T代表tighten，在rc的variation上的sigma分布比不帶T的更緊，因此只能用於setup，hold不推薦。Appleto Apple地比較，T的variation更小，理論看到的rc變化更小，單從setup產生violation的可能性更小。至於悲觀還是樂觀，除非自己定criteria，其余的follow foundry或者vendor的rule最重要。
Q：為什么setup既需要sign-off C-corner又需要sign-offRC-corner？
A：因為C-corner表示『電容』最大/最小，而RC-corner是『電容*電阻』最大/最小。通常對於短線而言，電容占主導地位，C-corner可以cover RC-corner，但對於長線則電阻占主導地位，C-corner無法cover RC-corner，而是反過來RC-corner去cover C-corner。而沒人保證一個設計里只有短線沒有長線，也沒權威對長短的幅度有量化的定義，所以最保險的就是兩者分別sign-off。
Q：為什么hold需要sign-off所有的corner？
A：對於hold而言，根據其仿真曲線，相互之間都無法完全覆蓋，故需要sign-off所有corner。
As you can see there is no empirical relationship. From a theoryperspective, density has to do with atomic packing and resistivity has to dowith electronic structure.
Iwill admit, however, that gaseous copper is an extremely poor conductor.
但是，在半導體制造過程中，由於工藝偏差，電阻跟金屬線的density是相關的。此時，電阻率是線寬跟線間距的函數。這一關系，在foundry給的工藝文件里都有相應的描述，這些都是在抽RC時需要考慮的因素。
Resistivity as a Function of Width and Spacing (Rs = f(W) or rho=f(W,S))
Variationin resistivity is caused by a number of phenomena. Copper is a softer materialthan the dielectric in which it is embedded. As a result, the polishing of thewafer during the CMP process has a tendency to remove a little extra copperfrom the top of the wire. This effect is called dishing because of the shape ofthe resulting wire top. The effect becomes more pronounced as the wire widthincreases. This effect is shown in exaggerated form in following pic.
To reduce theeffect of dishing on wide wires, small holes, or slots, can be inserted atregular intervals in wide wires. These slots insert a form of hard"posts" in the wire so that the CMP process removes less copper. Thistechnique reduces the dishing, as well as the effective resistivity.
Anothercontributor to resistivity variation is the cladding in copper wires. Claddingis the material grown around the sides and bottom of copper wires to protectthem from chemical reactions with the dielectric material. This cladding isillustrated in gray in following pic. The thickness ofthe cladding on the sides and bottoms of wires also varies with the width of awire. Because cladding has a much higher resistance than copper, it impacts theeffective resistivity of copper wires. This effect is more pronounced in thenarrowest wires. The combination of the effects ofdishing, slotting, and cladding thickness is modeled by the wire resistivity asa function of the wire width in silicon, and its spacing.
A：就電阻本身是跟spacing沒有無關的，但在半導體制造過程中，因為銅軟，所以在dishing時會把銅線切掉一些，這跟那個范圍的金屬線密度相關，而且這個關系好像也不是線性的。線的密度不同，會使得制造過程對線的厚度造成的影響不同，線厚度被改變了，那阻值自然被改變了。在QRC抽RC的時候會把這一效應模擬成『電阻率=f(W,S)』。 這一效應在foundry給的工藝文件里有相應的描述。
@SteveB 后端角度？如果講RC 后端抽怎么考慮，講好原理以后剩下的就是按照RC corner 加上溫度抽，交給工具。如果想要知道原理，有幾個方面可以去考慮，也是一般后端拿到新工藝需要去研究的:
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對於寄生參數提取，相關的各個工具的技術文件怎么來？
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每個corner下的配合PVT signoff里的T趨勢如何，是否可以對signoff做精簡 ？
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double pattern multiple pattern 的影響如何？
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研究DFM。
Q：為什么dpt之后多了ccworst跟ccbest？
A：@Fred ccbest和ccworst的出現是因為dpt同層metal分兩張mask，兩張mask的alignment誤差會導致兩張mask上相鄰的走線的間距變化，而造成電容的變化