Timing sign-off Corner = library PVT +RC Corner + OCV
針對每個工藝結點，foundry都會給出一張類似的timing sign-off表格，定義了所有需要做timing sign-off的corner（實際需要sign-off的corner還需要乘以工作模式，對於STA，不同的工作模式，用不同的SDC文件予以區別）
uncertainty=clock jitter + Xps setup/hold margin + DPT，其中clock jitter由用戶根據所用PLL的精度來確定；Xps由foundry提供，如：30ps for setup, 40ps for hold; DPT一項表示需要加的額外margin用於cover mask misalignment引起的偏差，該值亦由foundary提供，比如5ps for setup, 3ps for hold。
世界上沒有兩片相同的葉子，半導體世界里沒有兩只相同的管子。library中的cell delay是在某個固定的PVT（operating condition）下仿真得出的，也就是下圖中的Nominal delay，而實際上在芯片內部由於工藝偏差、電壓降、溫度變化，cell的delay並不是一個固定值，而是一個隨機值，遵循高斯分布或門特卡洛分布。
在STA中用OCV來模擬這一『特征』，OCV全稱on chip variation，用於描述不同管子間由於工藝偏差、電壓降、溫度變化引起的delay變化，也用於描述工藝偏差引起的net厚度寬度的變化從而導致net的電容電阻變化。
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PVT跟OCV都是用於描述Process、Voltage、Temperature對timing的影響，兩者有何區別？
PVT：主要取決於外部因素，在某一固定的工藝點、芯片的工作電壓、周圍環境溫度對芯片性能的影響。更直白的理解：同一顆芯片在不同工作電壓、環境溫度下的性能表現。
OCV：用於模擬芯片內部不同管子由於工藝偏差、電壓降、溫度變化引起的性能變化，這種變化更宏觀的表現是：不同芯片在相同PVT下的性能表現不同。
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在timing sign-off時，為什么要在Nominal delay上加OCV？
因為Nominal delay是在固定PVT下仿真得出的delay，而實際上由於OCV的影響，管子的delay是呈高斯分布或門特卡洛分布，要想保證yield，就必須在timing sign-off時將OCV考慮在內，以保證大部分管子都可以滿足時序要求。對每一代工藝，foundry都會做大量測試，針對每個corner找到一組適合的OCV值，這組值可以保證足夠高的yield，而如果進一步加緊這個值，並不會更有效的提高yield。在SOCV/POCV里的多少sigma(如：3-sigma)的選取也是出於相同的考慮
Interconnect variation: Another area of on-chip variation is in interconnect height and width, resulting in variation in both resistance and capacitance. Because the delay from interconnect is becoming more dominant as geometries shrink, you should pay attention to accurate modeling of interconnect variations. Two potential sources of this variation are the CMP (chemical-mechanical-planarization) process and the proximity effects in the photolithography and etch processes. Variation in the CMP process results from the difference in hardness between the interconnect material and the dielectric. Ideally, after the designer has etched trenches into the dielectric below an interconnect layer and copper on the wafer, the CMP process removes the unwanted copper, leaving only lines and vias. The copper line is softer than the dielectric material, resulting in "dishing" and erosion, which cause uneven removal of the copper and dielectric. Dishing is a function of line width and density, and erosion is a function of line space and density. Another source of variation in thickness due to CMP is a morerandom variation resulting in a gradient across the wafer. You can see thisgradient in die-to-die variations and even across-die variations for large die.You would ideally model this random, nondeterministic variation statistically.However, if you can obtain process data to model this variation, then you canmodel it deterministically as a function of position on the wafer. In thisscenario, you give an adder or subtracter, depending on the x,y position on thedie, to the RC value. Etch-proximity effects appear as "microloading," whichmeans that the etch process overetches isolated lines. A dual-damascenestructure uses only a single metal-deposition step to simultaneously form themain metal lines and the metal in the vias. That is, the formation of both thetrenches and the vias occurs in one dielectric layer. Overetching results in awider trench and, hence, a wider metal line. Photolithographic effects also cause problems. Diffraction andlocal scattering in photolithography may overexpose densely spaced lines andunderexpose isolated lines. Tiling and metal slotting reduce the variation infeature density and mitigate these effects. Tiling algorithms give differentresults, but a general rule states that a less dense gradient yields smallerline-width variations on the die. Tiling does have its drawbacks, however. Asone of the last integration steps in an SOC-design flow, tiling involvescalculations that the extractor performs using density parameters. Thesecalculations can result in different RC values before and after tiling. Tilingcan also result in small additional delay effects on timing. The final designmay not meet the desired target frequency once you account for tiling. Whetherit does depends largely on the design and the methods you use to meet thetiling requirements.
方法學上概念清晰了之后，EDA工具端的操作就十分簡單了，在EDA工具中如何設置OCV？每家工具都有各自不同的命令/變量控制，跟OCV相關的大致可分為四部分，此處以Tempus的命令為例：
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全局控制：set_analysis_mode -analysisType onChipVariation
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設置OCV：set_timing_derate -cell_delay/net_delay/cell_check -late/early -data/clock (1-d%)；其中d%是foundry在sign-off表格中給出的OCV值
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Report OCV: report_statistical_timing_derate_factors
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Debug timing時在timing report中將derate列顯示出來：set_global report_timing_format {instance arc delay slew arrival user_derate}
由於工藝的進步，flat OCV在先進工藝如16，7中已經逐步被AOCV, SOCV/POCV取代，以剔除悲觀度。